c3880c2c46
The routing algorithm is encapsulated in a separate SimObject to allow user to implement different routing strategies. The default implementation (WeightBased) maintains the original behavior. JIRA: https://gem5.atlassian.net/browse/GEM5-920 Change-Id: I5c8927f358b8b04b2da55e59679c2f629c7cd2f9 Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41858 Reviewed-by: Meatboy 106 <garbage2collector@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
133 lines
4.6 KiB
C++
133 lines
4.6 KiB
C++
/*
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* Copyright (c) 2020 Advanced Micro Devices, Inc.
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The topology here is configurable; it can be a hierachical (default
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* one) or a 2D torus or a 2D torus with half switches killed. I think
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* all input port has a one-input-one-output switch connected just to
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* control and bandwidth, since we don't control bandwidth on input
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* ports. Basically, the class has a vector of nodes and edges. First
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* 2*m_nodes elements in the node vector are input and output
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* ports. Edges are represented in two vectors of src and dest
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* nodes. All edges have latency.
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*/
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#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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#include <iostream>
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#include <vector>
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#include "mem/ruby/common/TypeDefines.hh"
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#include "mem/ruby/network/BasicLink.hh"
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#include "mem/ruby/protocol/LinkDirection.hh"
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namespace gem5
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{
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namespace ruby
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{
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class NetDest;
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class Network;
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/*
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* We use a three-dimensional vector matrix for calculating
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* the shortest paths for each pair of source and destination
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* and for each type of virtual network. The three dimensions
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* represent the source ID, destination ID, and vnet number.
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*/
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typedef std::vector<std::vector<std::vector<int>>> Matrix;
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struct LinkEntry
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{
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BasicLink *link;
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PortDirection src_outport_dirn;
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PortDirection dst_inport_dirn;
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};
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typedef std::map<std::pair<SwitchID, SwitchID>,
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std::vector<LinkEntry>> LinkMap;
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class Topology
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{
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public:
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Topology(uint32_t num_nodes, uint32_t num_routers, uint32_t num_vnets,
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const std::vector<BasicExtLink *> &ext_links,
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const std::vector<BasicIntLink *> &int_links);
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uint32_t numSwitches() const { return m_number_of_switches; }
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void createLinks(Network *net);
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void print(std::ostream& out) const { out << "[Topology]"; }
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private:
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void addLink(SwitchID src, SwitchID dest, BasicLink* link,
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PortDirection src_outport_dirn = "",
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PortDirection dest_inport_dirn = "");
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void makeLink(Network *net, SwitchID src, SwitchID dest,
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std::vector<NetDest>& routing_table_entry);
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// Helper functions based on chapter 29 of Cormen et al.
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void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies,
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Matrix &inter_switches);
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Matrix shortest_path(const Matrix &weights,
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Matrix &latencies, Matrix &inter_switches);
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bool link_is_shortest_path_to_node(SwitchID src, SwitchID next,
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SwitchID final, const Matrix &weights, const Matrix &dist,
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int vnet);
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NetDest shortest_path_to_node(SwitchID src, SwitchID next,
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const Matrix &weights, const Matrix &dist,
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int vnet);
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const uint32_t m_nodes;
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const uint32_t m_number_of_switches;
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int m_vnets;
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std::vector<BasicExtLink*> m_ext_link_vector;
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std::vector<BasicIntLink*> m_int_link_vector;
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LinkMap m_link_map;
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};
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inline std::ostream&
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operator<<(std::ostream& out, const Topology& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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} // namespace ruby
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} // namespace gem5
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#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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