0f90b7cb09
This will avoid having to create a new heap allocated PCState, since the instruction will know what type of backing storage to allocate on the stack for the working copy. Change-Id: Id208e015f6cb764bf7b13e0faf1677278b7e4641 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52069 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
96 lines
3.0 KiB
C++
96 lines
3.0 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/static_inst.hh"
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#include <iostream>
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#include "cpu/thread_context.hh"
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namespace gem5
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{
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StaticInstPtr
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StaticInst::fetchMicroop(MicroPC upc) const
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{
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panic("StaticInst::fetchMicroop() called on instruction "
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"that is not microcoded.");
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}
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std::unique_ptr<PCStateBase>
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StaticInst::branchTarget(const PCStateBase &pc) const
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{
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panic("StaticInst::branchTarget() called on instruction "
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"that is not a PC-relative branch.");
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}
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std::unique_ptr<PCStateBase>
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StaticInst::branchTarget(ThreadContext *tc) const
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{
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panic("StaticInst::branchTarget() called on instruction "
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"that is not an indirect branch.");
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}
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const std::string &
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StaticInst::disassemble(Addr pc, const loader::SymbolTable *symtab) const
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{
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if (!cachedDisassembly) {
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cachedDisassembly =
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std::make_unique<std::string>(generateDisassembly(pc, symtab));
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}
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return *cachedDisassembly;
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}
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void
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StaticInst::printFlags(std::ostream &outs,
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const std::string &separator) const
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{
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bool printed_a_flag = false;
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for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
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if (flags[flag]) {
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if (printed_a_flag)
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outs << separator;
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outs << FlagsStrings[flag];
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printed_a_flag = true;
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}
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}
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}
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void
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StaticInst::advancePC(ThreadContext *tc) const
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{
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std::unique_ptr<PCStateBase> pc(tc->pcState().clone());
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advancePC(*pc);
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tc->pcState(*pc);
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}
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} // namespace gem5
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