c2d2ea99e3
This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. --HG-- rename : src/mem/tport.cc => src/mem/packet_queue.cc rename : src/mem/tport.hh => src/mem/packet_queue.hh
93 lines
3.4 KiB
C++
93 lines
3.4 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "dev/x86/intdev.hh"
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void
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X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message,
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bool timing)
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{
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ApicList::iterator apicIt;
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for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
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PacketPtr pkt = buildIntRequest(*apicIt, message);
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if (timing) {
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queue.schedSendTiming(pkt, curTick() + latency);
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// The target handles cleaning up the packet in timing mode.
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} else {
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// ignore the latency involved in the atomic transaction
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sendAtomic(pkt);
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assert(pkt->isResponse());
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// also ignore the latency in handling the response
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recvResponse(pkt);
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delete pkt->req;
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delete pkt;
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}
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}
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}
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void
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X86ISA::IntDev::init()
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{
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if (!intPort.isConnected()) {
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panic("Int port not connected to anything!");
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}
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intPort.sendRangeChange();
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}
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X86ISA::IntSourcePin *
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X86IntSourcePinParams::create()
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{
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return new X86ISA::IntSourcePin(this);
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}
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X86ISA::IntSinkPin *
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X86IntSinkPinParams::create()
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{
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return new X86ISA::IntSinkPin(this);
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}
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X86ISA::IntLine *
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X86IntLineParams::create()
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{
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return new X86ISA::IntLine(this);
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}
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