Giacomo Travaglini c23c6ff50a dev-arm: Implement LevelSensitive PPIs in GICv3 ...

Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31516
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-07-23 16:51:03 +00:00

..

arch

arch-arm: Add System register trap check for EL1

2020-07-23 13:11:13 +00:00

base

base,arch: Fixed usage of bitfield::replaceBits

2020-07-22 05:17:33 +00:00

cpu

cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

2020-07-23 10:00:40 +00:00

dev

dev-arm: Implement LevelSensitive PPIs in GICv3

2020-07-23 16:51:03 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

misc,sim: Tagged API methods in sim/simobject.hh

2020-05-19 21:58:24 +00:00

gpu-compute

arch-gcn3,gpu-compute: Fix GCN3 related compiler errors

2020-07-20 14:53:13 +00:00

kern

arch,cpu,sim: Eliminate the now empty kernel statistics classes.

2020-06-17 19:54:41 +00:00

learning_gem5

misc: Make many includes explicit.

2020-06-03 19:42:46 +00:00

mem

mem: Use beats_per_clock as the DDR data rate for DRAMPower

2020-07-20 11:47:01 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

stats: add --stats-root option to dump only under some SimObjects

2020-07-01 13:22:52 +00:00

sim

sim: Add a ProxyPtr test.

2020-07-17 01:01:13 +00:00

systemc

systemc: Fix systemc array bound error

2020-07-22 20:10:09 +00:00

unittest

arch,base,cpu,kerm,sim: Build a symbol table for object files.

2020-06-09 23:37:29 +00:00

Doxyfile

misc: Reverting version numbers

2020-07-03 20:59:44 -07:00

SConscript

scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object

2020-06-22 09:08:42 +00:00