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c1a1f8ee95a6ed644838db06474801ba4b7bf124
gem5/arch
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Gabe Black 4f9ead58ff Clean up and fix for compilation
--HG--
extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
2006-03-17 14:02:38 -05:00
..
alpha
Merge m5.eecs.umich.edu:/bk/newmem
2006-03-16 14:08:31 -05:00
mips
fix to LiveProcess (this change got deleted somehow)
2006-03-16 19:01:09 -05:00
sparc
Clean up and fix for compilation
2006-03-17 14:02:38 -05:00
isa_parser.py
Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
2006-03-14 15:55:00 -05:00
isa_specific.hh
Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu
2006-03-14 18:28:51 -05:00
SConscript
Moved registerfile.hh to regfile.hh
2006-03-14 16:05:44 -05:00
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