Derek Christ
c13b79977c
Recent breaking changes in the DRAMSys API require user code to be updated. These updates have been applied to the gem5 integration. Furthermore, as DRAMSys started to use CMake dependency management, it is no longer sensible to maintain two separate build systems for DRAMSys. The use of the DRAMSys integration in gem5 will therefore from now on require that CMake is installed on the target machine. Additionally, support for snapshots have been implemented into DRAMSys and coupled with gem5's checkpointing API. Change-Id: I1ab25deba2a8478ff97c477694813ac123d60379
167 lines
5.9 KiB
Python
167 lines
5.9 KiB
Python
# -*- mode:python -*-
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#
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# Copyright (c) 2018-2020 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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SimObject('CommMonitor.py', sim_objects=['CommMonitor'])
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Source('comm_monitor.cc')
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SimObject('AbstractMemory.py', sim_objects=['AbstractMemory'])
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SimObject('AddrMapper.py', sim_objects=['AddrMapper', 'RangeAddrMapper'])
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SimObject('Bridge.py', sim_objects=['Bridge'])
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SimObject('SysBridge.py', sim_objects=['SysBridge'])
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DebugFlag('SysBridge')
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SimObject('MemCtrl.py', sim_objects=['MemCtrl'],
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enums=['MemSched'])
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SimObject('HeteroMemCtrl.py', sim_objects=['HeteroMemCtrl'])
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SimObject('HBMCtrl.py', sim_objects=['HBMCtrl'])
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SimObject('MemInterface.py', sim_objects=['MemInterface'], enums=['AddrMap'])
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SimObject('DRAMInterface.py', sim_objects=['DRAMInterface'],
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enums=['PageManage'])
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SimObject('NVMInterface.py', sim_objects=['NVMInterface'])
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SimObject('ExternalMaster.py', sim_objects=['ExternalMaster'])
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SimObject('ExternalSlave.py', sim_objects=['ExternalSlave'])
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SimObject('CfiMemory.py', sim_objects=['CfiMemory'])
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SimObject('SharedMemoryServer.py', sim_objects=['SharedMemoryServer'])
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SimObject('SimpleMemory.py', sim_objects=['SimpleMemory'])
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SimObject('XBar.py', sim_objects=[
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'BaseXBar', 'NoncoherentXBar', 'CoherentXBar', 'SnoopFilter'])
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SimObject('HMCController.py', sim_objects=['HMCController'])
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SimObject('SerialLink.py', sim_objects=['SerialLink'])
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SimObject('MemDelay.py', sim_objects=['MemDelay', 'SimpleMemDelay'])
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SimObject('PortTerminator.py', sim_objects=['PortTerminator'])
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SimObject('ThreadBridge.py', sim_objects=['ThreadBridge'])
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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Source('bridge.cc')
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Source('coherent_xbar.cc')
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Source('cfi_mem.cc')
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Source('drampower.cc')
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Source('external_master.cc')
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Source('external_slave.cc')
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Source('mem_ctrl.cc')
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Source('hetero_mem_ctrl.cc')
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Source('hbm_ctrl.cc')
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Source('mem_interface.cc')
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Source('dram_interface.cc')
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Source('nvm_interface.cc')
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Source('noncoherent_xbar.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('packet_queue.cc')
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Source('port_proxy.cc')
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Source('port_wrapper.cc')
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Source('physical.cc')
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Source('shared_memory_server.cc')
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Source('simple_mem.cc')
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Source('snoop_filter.cc')
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Source('stack_dist_calc.cc')
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Source('sys_bridge.cc')
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Source('thread_bridge.cc')
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Source('token_port.cc')
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Source('tport.cc')
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Source('xbar.cc')
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Source('hmc_controller.cc')
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Source('htm.cc')
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Source('serial_link.cc')
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Source('mem_delay.cc')
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Source('port_terminator.cc')
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GTest('translation_gen.test', 'translation_gen.test.cc')
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Source('translating_port_proxy.cc')
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Source('se_translating_port_proxy.cc')
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Source('page_table.cc')
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if env['HAVE_DRAMSIM']:
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SimObject('DRAMSim2.py', sim_objects=['DRAMSim2'])
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Source('dramsim2_wrapper.cc')
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Source('dramsim2.cc')
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if env['HAVE_DRAMSIM3']:
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SimObject('DRAMsim3.py', sim_objects=['DRAMsim3'])
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Source('dramsim3_wrapper.cc')
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Source('dramsim3.cc')
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if env['HAVE_DRAMSYS']:
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SimObject('DRAMSys.py', sim_objects=['DRAMSys'])
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Source('dramsys_wrapper.cc')
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Source('dramsys.cc')
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SimObject('MemChecker.py', sim_objects=['MemChecker', 'MemCheckerMonitor'])
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Source('mem_checker.cc')
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Source('mem_checker_monitor.cc')
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DebugFlag('AddrRanges')
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DebugFlag('BaseXBar')
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DebugFlag('CoherentXBar')
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DebugFlag('CFI')
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DebugFlag('NoncoherentXBar')
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DebugFlag('SnoopFilter')
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CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
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'SnoopFilter'])
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DebugFlag('Bridge')
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DebugFlag('CommMonitor')
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DebugFlag('DRAM')
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DebugFlag('DRAMPower')
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DebugFlag('DRAMState')
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DebugFlag('NVM')
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DebugFlag('ExternalPort')
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DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
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DebugFlag('LLSC')
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DebugFlag('MemCtrl')
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DebugFlag('MMU')
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DebugFlag('MemoryAccess')
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DebugFlag('PacketQueue')
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DebugFlag("PortTrace")
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DebugFlag('ResponsePort')
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DebugFlag('StackDist')
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DebugFlag("DRAMSim2")
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DebugFlag("DRAMsim3")
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DebugFlag('HMCController')
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DebugFlag('SerialLink')
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DebugFlag('TokenPort')
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DebugFlag("MemChecker")
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DebugFlag("MemCheckerMonitor")
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DebugFlag("QOS")
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