c0ab52799c
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
140 lines
5.7 KiB
Python
140 lines
5.7 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
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from Platform import Platform
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from Terminal import Terminal
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from Uart import Uart8250
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class MmDisk(BasicPioDevice):
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type = 'MmDisk'
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cxx_header = "dev/sparc/mm_disk.hh"
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image = Param.DiskImage("Disk Image")
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pio_addr = 0x1F40000000
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class DumbTOD(BasicPioDevice):
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type = 'DumbTOD'
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cxx_header = "dev/sparc/dtod.hh"
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time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
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pio_addr = 0xfff0c1fff8
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class Iob(PioDevice):
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type = 'Iob'
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cxx_header = "dev/sparc/iob.hh"
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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pio_latency = Param.Latency('1ns', "Programed IO latency")
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class T1000(Platform):
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type = 'T1000'
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cxx_header = "dev/sparc/t1000.hh"
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system = Param.System(Parent.any, "system")
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fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
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#warn_access="Accessing Clock Unit -- Unimplemented!")
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fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
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ret_data64=0x0000000000000000, update_data=False)
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#warn_access="Accessing Memory Banks -- Unimplemented!")
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fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
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#warn_access="Accessing JBI -- Unimplemented!")
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fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
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#warn_access="Accessing SSI -- Unimplemented!")
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hterm = Terminal()
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hvuart = Uart8250(pio_addr=0xfff0c2c000)
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htod = DumbTOD()
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pterm = Terminal()
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puart0 = Uart8250(pio_addr=0x1f10000000)
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iob = Iob()
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# Attach I/O devices that are on chip
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def attachOnChipIO(self, bus):
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self.iob.pio = bus.master
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self.htod.pio = bus.master
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.hvuart.terminal = self.hterm
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self.puart0.terminal = self.pterm
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self.fake_clk.pio = bus.master
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self.fake_membnks.pio = bus.master
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self.fake_l2_1.pio = bus.master
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self.fake_l2_2.pio = bus.master
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self.fake_l2_3.pio = bus.master
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self.fake_l2_4.pio = bus.master
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self.fake_l2esr_1.pio = bus.master
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self.fake_l2esr_2.pio = bus.master
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self.fake_l2esr_3.pio = bus.master
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self.fake_l2esr_4.pio = bus.master
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self.fake_ssi.pio = bus.master
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self.fake_jbi.pio = bus.master
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self.puart0.pio = bus.master
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self.hvuart.pio = bus.master
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