61d95de4c8
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
137 lines
2.7 KiB
C++
137 lines
2.7 KiB
C++
|
|
#include "cpu/beta_cpu/alpha_dyn_inst.hh"
|
|
|
|
template <class Impl>
|
|
AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
|
|
InstSeqNum seq_num, FullCPU *cpu)
|
|
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
|
{
|
|
// Make sure to have the renamed register entries set to the same
|
|
// as the normal register entries. It will allow the IQ to work
|
|
// without any modifications.
|
|
for (int i = 0; i < this->staticInst->numDestRegs(); i++)
|
|
{
|
|
_destRegIdx[i] = this->staticInst->destRegIdx(i);
|
|
}
|
|
|
|
for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
|
|
{
|
|
_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
|
|
this->_readySrcRegIdx[i] = 0;
|
|
}
|
|
|
|
}
|
|
|
|
template <class Impl>
|
|
AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
|
|
: BaseDynInst<Impl>(_staticInst)
|
|
{
|
|
// Make sure to have the renamed register entries set to the same
|
|
// as the normal register entries. It will allow the IQ to work
|
|
// without any modifications.
|
|
for (int i = 0; i < _staticInst->numDestRegs(); i++)
|
|
{
|
|
_destRegIdx[i] = _staticInst->destRegIdx(i);
|
|
}
|
|
|
|
for (int i = 0; i < _staticInst->numSrcRegs(); i++)
|
|
{
|
|
_srcRegIdx[i] = _staticInst->srcRegIdx(i);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
uint64_t
|
|
AlphaDynInst<Impl>::readUniq()
|
|
{
|
|
return this->cpu->readUniq();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaDynInst<Impl>::setUniq(uint64_t val)
|
|
{
|
|
this->cpu->setUniq(val);
|
|
}
|
|
|
|
template <class Impl>
|
|
uint64_t
|
|
AlphaDynInst<Impl>::readFpcr()
|
|
{
|
|
return this->cpu->readFpcr();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaDynInst<Impl>::setFpcr(uint64_t val)
|
|
{
|
|
this->cpu->setFpcr(val);
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
template <class Impl>
|
|
uint64_t
|
|
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
|
|
{
|
|
return this->cpu->readIpr(idx, fault);
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
|
|
{
|
|
return this->cpu->setIpr(idx, val);
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
AlphaDynInst<Impl>::hwrei()
|
|
{
|
|
return this->cpu->hwrei();
|
|
}
|
|
|
|
template <class Impl>
|
|
int
|
|
AlphaDynInst<Impl>::readIntrFlag()
|
|
{
|
|
return this->cpu->readIntrFlag();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaDynInst<Impl>::setIntrFlag(int val)
|
|
{
|
|
this->cpu->setIntrFlag(val);
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
AlphaDynInst<Impl>::inPalMode()
|
|
{
|
|
return this->cpu->inPalMode();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
AlphaDynInst<Impl>::trap(Fault fault)
|
|
{
|
|
this->cpu->trap(fault);
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
AlphaDynInst<Impl>::simPalCheck(int palFunc)
|
|
{
|
|
return this->cpu->simPalCheck(palFunc);
|
|
}
|
|
#else
|
|
template <class Impl>
|
|
void
|
|
AlphaDynInst<Impl>::syscall()
|
|
{
|
|
this->cpu->syscall(this->threadNumber);
|
|
// this->cpu->syscall();
|
|
}
|
|
#endif
|
|
|