In the SST integration the top of the main queue is checked for an event before starting the simulation. If the first event is scheduled after the ending tick, we are just returning the simulate_limit_event without entering the simulation loop. If the method is called with an empty queue, the following line will segfault (getHead() == nullptr): gem5::mainEventQueue[0]->getHead()->when() With this patch we are covering the case where we have an empty event queue Change-Id: I04463b45b269361172a9dd2fe1ba6e9428ac64f5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53723 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
472 lines
15 KiB
C++
472 lines
15 KiB
C++
// Copyright (c) 2021 The Regents of the University of California
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Copyright (c) 2015-2016 ARM Limited
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Copyright 2009-2014 Sandia Coporation. Under the terms
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// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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// Government retains certain rights in this software.
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//
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// Copyright (c) 2009-2014, Sandia Corporation
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// All rights reserved.
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//
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// For license information, see the LICENSE file in the current directory.
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#include <sst/core/sst_config.h>
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#include <sst/core/componentInfo.h>
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#include <sst/core/interfaces/simpleMem.h>
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#include <sst/elements/memHierarchy/memEvent.h>
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#include <sst/elements/memHierarchy/memTypes.h>
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#include <sst/elements/memHierarchy/util.h>
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#include <Python.h> // Before serialization to prevent spurious warnings
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#include "gem5.hh"
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#include "util.hh"
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// System headers
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#include <algorithm>
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#include <fstream>
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#include <iterator>
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#include <sstream>
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#include <string>
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#include <vector>
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// gem5 Headers
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#include <sim/core.hh>
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#include <sim/init.hh>
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#include <sim/init_signals.hh>
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#include <sim/root.hh>
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#include <sim/system.hh>
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#include <sim/sim_events.hh>
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#include <sim/sim_object.hh>
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#include <base/logging.hh>
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#include <base/debug.hh>
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#include <base/pollevent.hh>
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#include <base/types.hh>
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#include <sim/async.hh>
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#include <sim/eventq.hh>
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#include <sim/sim_exit.hh>
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#include <sim/stat_control.hh>
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#include <sst/outgoing_request_bridge.hh>
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#include <cassert>
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#ifdef fatal // gem5 sets this
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#undef fatal
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#endif
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// More SST Headers
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#include <core/timeConverter.h>
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gem5Component::gem5Component(SST::ComponentId_t id, SST::Params& params):
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SST::Component(id), threadInitialized(false)
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{
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output.init("gem5Component-" + getName() + "->", 1, 0,
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SST::Output::STDOUT);
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std::string cpu_frequency = params.find<std::string>("frequency", "");
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if (cpu_frequency.empty()) {
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output.fatal(
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CALL_INFO, -1, "The frequency of the CPU must be specified.\n"
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);
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}
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// Register a handler to be called on a set frequency.
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timeConverter = registerClock(
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cpu_frequency,
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new SST::Clock::Handler<gem5Component>(this, &gem5Component::clockTick)
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);
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// "cmd" -> gem5's Python
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std::string cmd = params.find<std::string>("cmd", "");
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if (cmd.empty()) {
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output.fatal(
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CALL_INFO, -1, "Component %s must have a 'cmd' parameter.\n",
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getName().c_str()
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);
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}
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// Telling SST the command line call to gem5
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args.push_back(const_cast<char*>("sst.x"));
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splitCommandArgs(cmd, args);
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output.output(CALL_INFO, "Command string: [sst.x %s]\n", cmd.c_str());
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for (size_t i = 0; i < args.size(); ++i) {
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output.output(CALL_INFO, " Arg [%02zu] = %s\n", i, args[i]);
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}
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// Parsing and setting gem5 debug flags
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std::string gem5_debug_flags = params.find<std::string>("debug_flags", "");
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for (auto const debug_flag: tokenizeString(gem5_debug_flags, {' ', ','})) {
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output.output(CALL_INFO, "Debug flag += %s\n", debug_flag.c_str());
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gem5::setDebugFlag(debug_flag.c_str());
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}
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registerAsPrimaryComponent();
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primaryComponentDoNotEndSim();
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systemPort = \
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loadUserSubComponent<SSTResponderSubComponent>("system_port",0);
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cachePort = \
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loadUserSubComponent<SSTResponderSubComponent>("cache_port", 0);
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systemPort->setTimeConverter(timeConverter);
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systemPort->setOutputStream(&(output));
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cachePort->setTimeConverter(timeConverter);
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cachePort->setOutputStream(&(output));
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}
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gem5Component::~gem5Component()
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{
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}
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void
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gem5Component::init(unsigned phase)
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{
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output.output(CALL_INFO," init phase: %u\n", phase);
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if (phase == 0) {
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initPython(args.size(), &args[0]);
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const std::vector<std::string> m5_instantiate_commands = {
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"m5.instantiate()"
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};
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execPythonCommands(m5_instantiate_commands);
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// calling SimObject.startup()
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const std::vector<std::string> simobject_setup_commands = {
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"import atexit",
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"import _m5",
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"root = m5.objects.Root.getInstance()",
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"for obj in root.descendants(): obj.startup()",
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"atexit.register(m5.stats.dump)",
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"atexit.register(_m5.core.doExitCleanup)",
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"m5.stats.reset()"
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};
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execPythonCommands(simobject_setup_commands);
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// find the corresponding SimObject for each SSTResponderSubComponent
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gem5::Root* gem5_root = gem5::Root::root();
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systemPort->findCorrespondingSimObject(gem5_root);
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cachePort->findCorrespondingSimObject(gem5_root);
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// initialize the gem5 event queue
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if (!(threadInitialized)) {
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threadInitialized = true;
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gem5::simulate_limit_event = new gem5::GlobalSimLoopExitEvent(
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gem5::mainEventQueue[0]->getCurTick(),
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"simulate() limit reached",
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0
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);
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}
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}
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systemPort->init(phase);
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cachePort->init(phase);
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}
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void
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gem5Component::setup()
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{
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output.verbose(CALL_INFO, 1, 0, "Component is being setup.\n");
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systemPort->setup();
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cachePort->setup();
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}
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void
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gem5Component::finish()
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{
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output.verbose(CALL_INFO, 1, 0, "Component is being finished.\n");
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}
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bool
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gem5Component::clockTick(SST::Cycle_t currentCycle)
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{
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// what to do in a SST's cycle
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gem5::GlobalSimLoopExitEvent *event = simulateGem5(currentCycle);
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clocksProcessed++;
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// gem5 exits due to reasons other than reaching simulation limit
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if (event != gem5::simulate_limit_event) {
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output.output("exiting: curTick()=%lu cause=`%s` code=%d\n",
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gem5::curTick(), event->getCause().c_str(), event->getCode()
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);
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// output gem5 stats
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const std::vector<std::string> output_stats_commands = {
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"m5.stats.dump()"
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};
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execPythonCommands(output_stats_commands);
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primaryComponentOKToEndSim();
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return true;
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}
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// returning False means the simulation should go on
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return false;
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}
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#define PyCC(x) (const_cast<char *>(x))
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gem5::GlobalSimLoopExitEvent*
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gem5Component::simulateGem5(uint64_t current_cycle)
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{
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// This function should be similar to simulate() of src/sim/simulate.cc
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// with synchronization barriers removed.
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inform_once("Entering event queue @ %d. Starting simulation...\n",
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gem5::curTick());
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// Tick conversion
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// The main logic for synchronize SST Tick and gem5 Tick is here.
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// next_end_tick = current_cycle * timeConverter->getFactor()
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uint64_t next_end_tick = \
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timeConverter->convertToCoreTime(current_cycle);
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// Here, if the next event in gem5's queue is not executed within the next
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// cycle, there's no need to enter the gem5's sim loop.
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if (gem5::mainEventQueue[0]->empty() ||
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next_end_tick < gem5::mainEventQueue[0]->getHead()->when()) {
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return gem5::simulate_limit_event;
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}
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gem5::simulate_limit_event->reschedule(next_end_tick);
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gem5::Event *local_event = doSimLoop(gem5::mainEventQueue[0]);
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gem5::BaseGlobalEvent *global_event = local_event->globalEvent();
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gem5::GlobalSimLoopExitEvent *global_exit_event =
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dynamic_cast<gem5::GlobalSimLoopExitEvent *>(global_event);
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return global_exit_event;
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}
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gem5::Event*
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gem5Component::doSimLoop(gem5::EventQueue* eventq)
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{
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// This function should be similar to doSimLoop() in src/sim/simulate.cc
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// with synchronization barriers removed.
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gem5::curEventQueue(eventq);
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eventq->handleAsyncInsertions();
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while (true)
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{
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// there should always be at least one event (the SimLoopExitEvent
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// we just scheduled) in the queue
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assert(!eventq->empty());
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assert(gem5::curTick() <= eventq->nextTick() &&
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"event scheduled in the past");
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if (gem5::async_event) {
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// Take the event queue lock in case any of the service
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// routines want to schedule new events.
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if (gem5::async_statdump || gem5::async_statreset) {
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gem5::statistics::schedStatEvent(gem5::async_statdump,
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gem5::async_statreset);
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gem5::async_statdump = false;
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gem5::async_statreset = false;
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}
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if (gem5::async_io) {
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gem5::async_io = false;
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gem5::pollQueue.service();
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}
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if (gem5::async_exit) {
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gem5::async_exit = false;
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gem5::exitSimLoop("user interrupt received");
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}
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if (gem5::async_exception) {
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gem5::async_exception = false;
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return NULL;
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}
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}
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gem5::Event *exit_event = eventq->serviceOne();
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if (exit_event != NULL) {
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return exit_event;
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}
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}
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}
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int
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gem5Component::execPythonCommands(const std::vector<std::string>& commands)
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{
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PyObject *dict = PyModule_GetDict(pythonMain);
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PyObject *result;
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for (auto const command: commands) {
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result = PyRun_String(command.c_str(), Py_file_input, dict, dict);
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if (!result) {
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PyErr_Print();
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return 1;
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}
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Py_DECREF(result);
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}
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return 0;
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}
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int
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gem5Component::startM5(int argc, char **_argv)
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{
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// This function should be similar to m5Main() of src/sim/init.cc
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#if HAVE_PROTOBUF
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// Verify that the version of the protobuf library that we linked
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// against is compatible with the version of the headers we
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// compiled against.
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GOOGLE_PROTOBUF_VERIFY_VERSION;
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#endif
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#if PY_MAJOR_VERSION >= 3
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typedef std::unique_ptr<wchar_t[], decltype(&PyMem_RawFree)> WArgUPtr;
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std::vector<WArgUPtr> v_argv;
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std::vector<wchar_t *> vp_argv;
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v_argv.reserve(argc);
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vp_argv.reserve(argc);
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for (int i = 0; i < argc; i++) {
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v_argv.emplace_back(Py_DecodeLocale(_argv[i], NULL), &PyMem_RawFree);
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vp_argv.emplace_back(v_argv.back().get());
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}
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wchar_t **argv = vp_argv.data();
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#else
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char **argv = _argv;
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#endif
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PySys_SetArgv(argc, argv);
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// We have to set things up in the special __main__ module
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pythonMain = PyImport_AddModule(PyCC("__main__"));
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if (pythonMain == NULL)
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panic("Could not import __main__");
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const std::vector<std::string> commands = {
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"import m5",
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"m5.main()"
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};
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execPythonCommands(commands);
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#if HAVE_PROTOBUF
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google::protobuf::ShutdownProtobufLibrary();
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#endif
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return 0;
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}
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void
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gem5Component::initPython(int argc, char *_argv[])
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{
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// should be similar to main() in src/sim/main.cc
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PyObject *mainModule, *mainDict;
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int ret;
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// Initialize m5 special signal handling.
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gem5::initSignals();
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#if PY_MAJOR_VERSION >= 3
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std::unique_ptr<wchar_t[], decltype(&PyMem_RawFree)> program(
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Py_DecodeLocale(_argv[0], NULL),
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&PyMem_RawFree);
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Py_SetProgramName(program.get());
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#else
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Py_SetProgramName(_argv[0]);
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#endif
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// Register native modules with Python's init system before
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// initializing the interpreter.
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if (!Py_IsInitialized()) {
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gem5::registerNativeModules();
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// initialize embedded Python interpreter
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Py_Initialize();
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} else {
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// https://stackoverflow.com/a/28349174
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PyImport_AddModule("_m5");
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PyObject* module = gem5::EmbeddedPyBind::initAll();
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PyObject* sys_modules = PyImport_GetModuleDict();
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PyDict_SetItemString(sys_modules, "_m5", module);
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Py_DECREF(module);
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}
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// Initialize the embedded m5 python library
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ret = gem5::EmbeddedPython::initAll();
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if (ret == 0)
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startM5(argc, _argv); // start m5
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else
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output.output(CALL_INFO, "Not calling m5Main due to ret=%d\n", ret);
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}
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void
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gem5Component::splitCommandArgs(std::string &cmd, std::vector<char*> &args)
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{
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std::vector<std::string> parsed_args = tokenizeString(
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cmd, {'\\', ' ', '\'', '\"'}
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);
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for (auto part: parsed_args)
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args.push_back(strdup(part.c_str()));
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}
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