Giacomo Travaglini 7ce081d583 misc: Remove any reference to the ALPHA ISA ...

Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-06-08 09:00:55 +00:00

..

arm-ccregs.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

arm-contextidr-el2.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

arm-gem5-gic-ext.py

util: Delete authors lists from files in util.

2020-02-18 10:24:43 +00:00

arm-gicv2-banked-regs.py

arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling

2017-04-03 16:51:46 +00:00

arm-hdlcd-upgrade.py

util: Make cpt_upgraders python3 compatible

2020-05-06 08:15:15 +00:00

arm-miscreg-teehbr.py

util: Make cpt_upgraders python3 compatible

2020-05-06 08:15:15 +00:00

arm-sve.py

util: Make cpt_upgraders python3 compatible

2020-05-06 08:15:15 +00:00

arm-sysreg-mapping-ns.py

arm: update AArch{64,32} register mappings

2016-12-19 11:03:27 -06:00

armv8.py

util: Make cpt_upgraders python3 compatible

2020-05-06 08:15:15 +00:00

cpu-pid.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

dvfs-perflevel.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

etherswitch.py

dist, dev: fix etherswitch upgrade script

2016-12-19 12:12:28 -06:00

ide-dma-abort.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

isa-is-simobject.py

misc: Remove any reference to the ALPHA ISA

2020-06-08 09:00:55 +00:00

memory-per-range.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

multiple-event-queues.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

process-fdmap-rename.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

remove-arm-cpsr-mode-miscreg.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

ruby-block-size-bytes.py

sim: tag-based checkpoint versioning

2015-09-02 15:23:30 -05:00

smt-interrupts.py

isa,cpu: Add support for FS SMT Interrupts

2015-09-30 11:14:19 -05:00

x86-add-tlb.py

util: Make cpt_upgraders python3 compatible

2020-05-06 08:15:15 +00:00