bb9d2c3457
O can move to my laptop.
tests/SConscript:
Start to simplify.
--HG--
rename : tests/test1/ref/alpha/detailed/config.ini => tests/quick/eio1/ref/alpha/eio/detailed/config.ini
rename : tests/test1/ref/alpha/detailed/config.out => tests/quick/eio1/ref/alpha/eio/detailed/config.out
rename : tests/test1/ref/alpha/detailed/m5stats.txt => tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt
rename : tests/test1/ref/alpha/detailed/stderr => tests/quick/eio1/ref/alpha/eio/detailed/stderr
rename : tests/test1/ref/alpha/detailed/stdout => tests/quick/eio1/ref/alpha/eio/detailed/stdout
rename : tests/test1/ref/alpha/atomic/config.ini => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini
rename : tests/test1/ref/alpha/atomic/config.out => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out
rename : tests/test1/ref/alpha/atomic/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/test1/ref/alpha/atomic/stderr => tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr
rename : tests/test1/ref/alpha/atomic/stdout => tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout
rename : tests/test1/ref/alpha/timing/config.ini => tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini
rename : tests/test1/ref/alpha/timing/config.out => tests/quick/eio1/ref/alpha/eio/simple-timing/config.out
rename : tests/test1/ref/alpha/timing/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/test1/ref/alpha/timing/stderr => tests/quick/eio1/ref/alpha/eio/simple-timing/stderr
rename : tests/test1/ref/alpha/timing/stdout => tests/quick/eio1/ref/alpha/eio/simple-timing/stdout
extra : convert_revision : 924d2ee29d2a2709135ff8e5c5822fe47a8a60f6
15 lines
370 B
Python
15 lines
370 B
Python
import m5
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from m5.objects import *
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m5.AddToPath('../configs/common')
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from SEConfig import *
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system = System(cpu = AtomicSimpleCPU(),
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physmem = PhysicalMemory(),
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membus = Bus())
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system.physmem.port = system.membus.port
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system.cpu.icache_port = system.membus.port
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system.cpu.dcache_port = system.membus.port
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root = Root(system = system)
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