babf072c1c
This patch adds a state machine for the refresh scheduling to ensure that no accesses are allowed while the refresh is in progress, and that all banks are propely precharged. As part of this change, the precharging of banks of broken out into a method of its own, making is similar to how activations are dealt with. The idle accounting is also updated to ensure that the refresh duration is not added to the time that the DRAM is in the idle state with all banks precharged.
1848 lines
64 KiB
C++
1848 lines
64 KiB
C++
/*
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* Copyright (c) 2010-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Ani Udipi
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* Neha Agarwal
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*/
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "debug/DRAM.hh"
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#include "debug/Drain.hh"
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#include "mem/dram_ctrl.hh"
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#include "sim/system.hh"
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using namespace std;
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DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
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AbstractMemory(p),
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port(name() + ".port", *this),
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retryRdReq(false), retryWrReq(false),
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rowHitFlag(false), busState(READ),
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respondEvent(this), refreshEvent(this),
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nextReqEvent(this), drainManager(NULL),
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deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
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deviceRowBufferSize(p->device_rowbuffer_size),
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devicesPerRank(p->devices_per_rank),
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burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
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rowBufferSize(devicesPerRank * deviceRowBufferSize),
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columnsPerRowBuffer(rowBufferSize / burstSize),
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ranksPerChannel(p->ranks_per_channel),
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banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
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readBufferSize(p->read_buffer_size),
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writeBufferSize(p->write_buffer_size),
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writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
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writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
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minWritesPerSwitch(p->min_writes_per_switch),
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writesThisTime(0), readsThisTime(0),
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tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
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tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
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tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
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tXAW(p->tXAW), activationLimit(p->activation_limit),
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memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
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pageMgmt(p->page_policy),
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maxAccessesPerRow(p->max_accesses_per_row),
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frontendLatency(p->static_frontend_latency),
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backendLatency(p->static_backend_latency),
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busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), prevArrival(0),
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nextReqTime(0), idleStartTick(0), numBanksActive(0)
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{
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// create the bank states based on the dimensions of the ranks and
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// banks
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banks.resize(ranksPerChannel);
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actTicks.resize(ranksPerChannel);
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for (size_t c = 0; c < ranksPerChannel; ++c) {
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banks[c].resize(banksPerRank);
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actTicks[c].resize(activationLimit, 0);
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}
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// perform a basic check of the write thresholds
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if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
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fatal("Write buffer low threshold %d must be smaller than the "
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"high threshold %d\n", p->write_low_thresh_perc,
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p->write_high_thresh_perc);
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// determine the rows per bank by looking at the total capacity
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uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
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DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
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AbstractMemory::size());
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DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
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rowBufferSize, columnsPerRowBuffer);
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rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
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if (range.interleaved()) {
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if (channels != range.stripes())
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fatal("%s has %d interleaved address stripes but %d channel(s)\n",
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name(), range.stripes(), channels);
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if (addrMapping == Enums::RoRaBaChCo) {
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if (rowBufferSize != range.granularity()) {
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fatal("Interleaving of %s doesn't match RoRaBaChCo "
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"address map\n", name());
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}
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} else if (addrMapping == Enums::RoRaBaCoCh) {
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if (system()->cacheLineSize() != range.granularity()) {
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fatal("Interleaving of %s doesn't match RoRaBaCoCh "
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"address map\n", name());
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}
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} else if (addrMapping == Enums::RoCoRaBaCh) {
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if (system()->cacheLineSize() != range.granularity())
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fatal("Interleaving of %s doesn't match RoCoRaBaCh "
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"address map\n", name());
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}
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}
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// some basic sanity checks
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if (tREFI <= tRP || tREFI <= tRFC) {
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fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
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tREFI, tRP, tRFC);
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}
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}
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void
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DRAMCtrl::init()
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{
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if (!port.isConnected()) {
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fatal("DRAMCtrl %s is unconnected!\n", name());
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} else {
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port.sendRangeChange();
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}
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}
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void
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DRAMCtrl::startup()
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{
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// update the start tick for the precharge accounting to the
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// current tick
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idleStartTick = curTick();
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// shift the bus busy time sufficiently far ahead that we never
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// have to worry about negative values when computing the time for
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// the next request, this will add an insignificant bubble at the
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// start of simulation
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busBusyUntil = curTick() + tRP + tRCD + tCL;
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// print the configuration of the controller
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printParams();
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// kick off the refresh, and give ourselves enough time to
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// precharge
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schedule(refreshEvent, curTick() + tREFI - tRP);
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}
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Tick
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DRAMCtrl::recvAtomic(PacketPtr pkt)
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{
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DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
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// do the actual memory access and turn the packet into a response
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access(pkt);
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Tick latency = 0;
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if (!pkt->memInhibitAsserted() && pkt->hasData()) {
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// this value is not supposed to be accurate, just enough to
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// keep things going, mimic a closed page
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latency = tRP + tRCD + tCL;
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}
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return latency;
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}
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bool
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DRAMCtrl::readQueueFull(unsigned int neededEntries) const
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{
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DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
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readBufferSize, readQueue.size() + respQueue.size(),
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neededEntries);
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return
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(readQueue.size() + respQueue.size() + neededEntries) > readBufferSize;
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}
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bool
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DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
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{
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DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
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writeBufferSize, writeQueue.size(), neededEntries);
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return (writeQueue.size() + neededEntries) > writeBufferSize;
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}
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DRAMCtrl::DRAMPacket*
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DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
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bool isRead)
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{
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// decode the address based on the address mapping scheme, with
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// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
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// channel, respectively
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uint8_t rank;
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uint8_t bank;
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uint16_t row;
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// truncate the address to the access granularity
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Addr addr = dramPktAddr / burstSize;
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// we have removed the lowest order address bits that denote the
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// position within the column
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if (addrMapping == Enums::RoRaBaChCo) {
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// the lowest order bits denote the column to ensure that
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// sequential cache lines occupy the same row
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addr = addr / columnsPerRowBuffer;
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// take out the channel part of the address
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addr = addr / channels;
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// after the channel bits, get the bank bits to interleave
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// over the banks
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// after the bank, we get the rank bits which thus interleaves
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// over the ranks
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// lastly, get the row bits
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row = addr % rowsPerBank;
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addr = addr / rowsPerBank;
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} else if (addrMapping == Enums::RoRaBaCoCh) {
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// take out the channel part of the address
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addr = addr / channels;
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// next, the column
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addr = addr / columnsPerRowBuffer;
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// after the column bits, we get the bank bits to interleave
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// over the banks
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// after the bank, we get the rank bits which thus interleaves
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// over the ranks
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// lastly, get the row bits
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row = addr % rowsPerBank;
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addr = addr / rowsPerBank;
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} else if (addrMapping == Enums::RoCoRaBaCh) {
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// optimise for closed page mode and utilise maximum
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// parallelism of the DRAM (at the cost of power)
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// take out the channel part of the address, not that this has
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// to match with how accesses are interleaved between the
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// controllers in the address mapping
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addr = addr / channels;
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// start with the bank bits, as this provides the maximum
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// opportunity for parallelism between requests
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// next get the rank bits
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// next the column bits which we do not need to keep track of
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// and simply skip past
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addr = addr / columnsPerRowBuffer;
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// lastly, get the row bits
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row = addr % rowsPerBank;
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addr = addr / rowsPerBank;
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} else
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panic("Unknown address mapping policy chosen!");
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assert(rank < ranksPerChannel);
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assert(bank < banksPerRank);
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assert(row < rowsPerBank);
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DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
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dramPktAddr, rank, bank, row);
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// create the corresponding DRAM packet with the entry time and
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// ready time set to the current tick, the latter will be updated
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// later
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uint16_t bank_id = banksPerRank * rank + bank;
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return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
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size, banks[rank][bank]);
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}
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void
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DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
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{
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// only add to the read queue here. whenever the request is
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// eventually done, set the readyTime, and call schedule()
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assert(!pkt->isWrite());
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assert(pktCount != 0);
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// if the request size is larger than burst size, the pkt is split into
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// multiple DRAM packets
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// Note if the pkt starting address is not aligened to burst size, the
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// address of first DRAM packet is kept unaliged. Subsequent DRAM packets
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// are aligned to burst size boundaries. This is to ensure we accurately
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// check read packets against packets in write queue.
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Addr addr = pkt->getAddr();
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unsigned pktsServicedByWrQ = 0;
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BurstHelper* burst_helper = NULL;
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for (int cnt = 0; cnt < pktCount; ++cnt) {
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unsigned size = std::min((addr | (burstSize - 1)) + 1,
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pkt->getAddr() + pkt->getSize()) - addr;
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readPktSize[ceilLog2(size)]++;
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readBursts++;
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// First check write buffer to see if the data is already at
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// the controller
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bool foundInWrQ = false;
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for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) {
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// check if the read is subsumed in the write entry we are
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// looking at
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if ((*i)->addr <= addr &&
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(addr + size) <= ((*i)->addr + (*i)->size)) {
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foundInWrQ = true;
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servicedByWrQ++;
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pktsServicedByWrQ++;
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DPRINTF(DRAM, "Read to addr %lld with size %d serviced by "
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"write queue\n", addr, size);
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bytesReadWrQ += burstSize;
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break;
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}
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}
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// If not found in the write q, make a DRAM packet and
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// push it onto the read queue
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if (!foundInWrQ) {
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// Make the burst helper for split packets
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if (pktCount > 1 && burst_helper == NULL) {
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DPRINTF(DRAM, "Read to addr %lld translates to %d "
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"dram requests\n", pkt->getAddr(), pktCount);
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burst_helper = new BurstHelper(pktCount);
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}
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DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
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dram_pkt->burstHelper = burst_helper;
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assert(!readQueueFull(1));
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rdQLenPdf[readQueue.size() + respQueue.size()]++;
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DPRINTF(DRAM, "Adding to read queue\n");
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readQueue.push_back(dram_pkt);
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// Update stats
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avgRdQLen = readQueue.size() + respQueue.size();
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}
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// Starting address of next dram pkt (aligend to burstSize boundary)
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addr = (addr | (burstSize - 1)) + 1;
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}
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// If all packets are serviced by write queue, we send the repsonse back
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if (pktsServicedByWrQ == pktCount) {
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accessAndRespond(pkt, frontendLatency);
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return;
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}
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// Update how many split packets are serviced by write queue
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if (burst_helper != NULL)
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burst_helper->burstsServiced = pktsServicedByWrQ;
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// If we are not already scheduled to get a request out of the
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// queue, do so now
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if (!nextReqEvent.scheduled()) {
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DPRINTF(DRAM, "Request scheduled immediately\n");
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schedule(nextReqEvent, curTick());
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}
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}
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void
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DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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{
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// only add to the write queue here. whenever the request is
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// eventually done, set the readyTime, and call schedule()
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assert(pkt->isWrite());
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// if the request size is larger than burst size, the pkt is split into
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// multiple DRAM packets
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Addr addr = pkt->getAddr();
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for (int cnt = 0; cnt < pktCount; ++cnt) {
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unsigned size = std::min((addr | (burstSize - 1)) + 1,
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pkt->getAddr() + pkt->getSize()) - addr;
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writePktSize[ceilLog2(size)]++;
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writeBursts++;
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// see if we can merge with an existing item in the write
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// queue and keep track of whether we have merged or not so we
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// can stop at that point and also avoid enqueueing a new
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// request
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bool merged = false;
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auto w = writeQueue.begin();
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while(!merged && w != writeQueue.end()) {
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// either of the two could be first, if they are the same
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// it does not matter which way we go
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if ((*w)->addr >= addr) {
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// the existing one starts after the new one, figure
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// out where the new one ends with respect to the
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// existing one
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if ((addr + size) >= ((*w)->addr + (*w)->size)) {
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// check if the existing one is completely
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// subsumed in the new one
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DPRINTF(DRAM, "Merging write covering existing burst\n");
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merged = true;
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// update both the address and the size
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(*w)->addr = addr;
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(*w)->size = size;
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} else if ((addr + size) >= (*w)->addr &&
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((*w)->addr + (*w)->size - addr) <= burstSize) {
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// the new one is just before or partially
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// overlapping with the existing one, and together
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// they fit within a burst
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DPRINTF(DRAM, "Merging write before existing burst\n");
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merged = true;
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// the existing queue item needs to be adjusted with
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// respect to both address and size
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(*w)->size = (*w)->addr + (*w)->size - addr;
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(*w)->addr = addr;
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}
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} else {
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// the new one starts after the current one, figure
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// out where the existing one ends with respect to the
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// new one
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if (((*w)->addr + (*w)->size) >= (addr + size)) {
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// check if the new one is completely subsumed in the
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// existing one
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DPRINTF(DRAM, "Merging write into existing burst\n");
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merged = true;
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// no adjustments necessary
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} else if (((*w)->addr + (*w)->size) >= addr &&
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(addr + size - (*w)->addr) <= burstSize) {
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// the existing one is just before or partially
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// overlapping with the new one, and together
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// they fit within a burst
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DPRINTF(DRAM, "Merging write after existing burst\n");
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merged = true;
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// the address is right, and only the size has
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// to be adjusted
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(*w)->size = addr + size - (*w)->addr;
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}
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}
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++w;
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}
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// if the item was not merged we need to create a new write
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// and enqueue it
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if (!merged) {
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DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
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assert(writeQueue.size() < writeBufferSize);
|
|
wrQLenPdf[writeQueue.size()]++;
|
|
|
|
DPRINTF(DRAM, "Adding to write queue\n");
|
|
|
|
writeQueue.push_back(dram_pkt);
|
|
|
|
// Update stats
|
|
avgWrQLen = writeQueue.size();
|
|
} else {
|
|
// keep track of the fact that this burst effectively
|
|
// disappeared as it was merged with an existing one
|
|
mergedWrBursts++;
|
|
}
|
|
|
|
// Starting address of next dram pkt (aligend to burstSize boundary)
|
|
addr = (addr | (burstSize - 1)) + 1;
|
|
}
|
|
|
|
// we do not wait for the writes to be send to the actual memory,
|
|
// but instead take responsibility for the consistency here and
|
|
// snoop the write queue for any upcoming reads
|
|
// @todo, if a pkt size is larger than burst size, we might need a
|
|
// different front end latency
|
|
accessAndRespond(pkt, frontendLatency);
|
|
|
|
// If we are not already scheduled to get a request out of the
|
|
// queue, do so now
|
|
if (!nextReqEvent.scheduled()) {
|
|
DPRINTF(DRAM, "Request scheduled immediately\n");
|
|
schedule(nextReqEvent, curTick());
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::printParams() const
|
|
{
|
|
// Sanity check print of important parameters
|
|
DPRINTF(DRAM,
|
|
"Memory controller %s physical organization\n" \
|
|
"Number of devices per rank %d\n" \
|
|
"Device bus width (in bits) %d\n" \
|
|
"DRAM data bus burst (bytes) %d\n" \
|
|
"Row buffer size (bytes) %d\n" \
|
|
"Columns per row buffer %d\n" \
|
|
"Rows per bank %d\n" \
|
|
"Banks per rank %d\n" \
|
|
"Ranks per channel %d\n" \
|
|
"Total mem capacity (bytes) %u\n",
|
|
name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize,
|
|
columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel,
|
|
rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel);
|
|
|
|
string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS";
|
|
string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" :
|
|
(addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh");
|
|
string page_policy = pageMgmt == Enums::open ? "OPEN" :
|
|
(pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" :
|
|
(pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE"));
|
|
|
|
DPRINTF(DRAM,
|
|
"Memory controller %s characteristics\n" \
|
|
"Read buffer size %d\n" \
|
|
"Write buffer size %d\n" \
|
|
"Write high thresh %d\n" \
|
|
"Write low thresh %d\n" \
|
|
"Scheduler %s\n" \
|
|
"Address mapping %s\n" \
|
|
"Page policy %s\n",
|
|
name(), readBufferSize, writeBufferSize, writeHighThreshold,
|
|
writeLowThreshold, scheduler, address_mapping, page_policy);
|
|
|
|
DPRINTF(DRAM, "Memory controller %s timing specs\n" \
|
|
"tRCD %d ticks\n" \
|
|
"tCL %d ticks\n" \
|
|
"tRP %d ticks\n" \
|
|
"tBURST %d ticks\n" \
|
|
"tRFC %d ticks\n" \
|
|
"tREFI %d ticks\n" \
|
|
"tWTR %d ticks\n" \
|
|
"tRTW %d ticks\n" \
|
|
"tXAW (%d) %d ticks\n",
|
|
name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR,
|
|
tRTW, activationLimit, tXAW);
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::printQs() const {
|
|
DPRINTF(DRAM, "===READ QUEUE===\n\n");
|
|
for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
|
|
DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
|
|
}
|
|
DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
|
|
for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) {
|
|
DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
|
|
}
|
|
DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
|
|
for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) {
|
|
DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
|
|
}
|
|
}
|
|
|
|
bool
|
|
DRAMCtrl::recvTimingReq(PacketPtr pkt)
|
|
{
|
|
/// @todo temporary hack to deal with memory corruption issues until
|
|
/// 4-phase transactions are complete
|
|
for (int x = 0; x < pendingDelete.size(); x++)
|
|
delete pendingDelete[x];
|
|
pendingDelete.clear();
|
|
|
|
// This is where we enter from the outside world
|
|
DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
|
|
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
|
|
|
|
// simply drop inhibited packets for now
|
|
if (pkt->memInhibitAsserted()) {
|
|
DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n");
|
|
pendingDelete.push_back(pkt);
|
|
return true;
|
|
}
|
|
|
|
// Calc avg gap between requests
|
|
if (prevArrival != 0) {
|
|
totGap += curTick() - prevArrival;
|
|
}
|
|
prevArrival = curTick();
|
|
|
|
|
|
// Find out how many dram packets a pkt translates to
|
|
// If the burst size is equal or larger than the pkt size, then a pkt
|
|
// translates to only one dram packet. Otherwise, a pkt translates to
|
|
// multiple dram packets
|
|
unsigned size = pkt->getSize();
|
|
unsigned offset = pkt->getAddr() & (burstSize - 1);
|
|
unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
|
|
|
|
// check local buffers and do not accept if full
|
|
if (pkt->isRead()) {
|
|
assert(size != 0);
|
|
if (readQueueFull(dram_pkt_count)) {
|
|
DPRINTF(DRAM, "Read queue full, not accepting\n");
|
|
// remember that we have to retry this port
|
|
retryRdReq = true;
|
|
numRdRetry++;
|
|
return false;
|
|
} else {
|
|
addToReadQueue(pkt, dram_pkt_count);
|
|
readReqs++;
|
|
bytesReadSys += size;
|
|
}
|
|
} else if (pkt->isWrite()) {
|
|
assert(size != 0);
|
|
if (writeQueueFull(dram_pkt_count)) {
|
|
DPRINTF(DRAM, "Write queue full, not accepting\n");
|
|
// remember that we have to retry this port
|
|
retryWrReq = true;
|
|
numWrRetry++;
|
|
return false;
|
|
} else {
|
|
addToWriteQueue(pkt, dram_pkt_count);
|
|
writeReqs++;
|
|
bytesWrittenSys += size;
|
|
}
|
|
} else {
|
|
DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
|
|
neitherReadNorWrite++;
|
|
accessAndRespond(pkt, 1);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::processRespondEvent()
|
|
{
|
|
DPRINTF(DRAM,
|
|
"processRespondEvent(): Some req has reached its readyTime\n");
|
|
|
|
DRAMPacket* dram_pkt = respQueue.front();
|
|
|
|
if (dram_pkt->burstHelper) {
|
|
// it is a split packet
|
|
dram_pkt->burstHelper->burstsServiced++;
|
|
if (dram_pkt->burstHelper->burstsServiced ==
|
|
dram_pkt->burstHelper->burstCount) {
|
|
// we have now serviced all children packets of a system packet
|
|
// so we can now respond to the requester
|
|
// @todo we probably want to have a different front end and back
|
|
// end latency for split packets
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
delete dram_pkt->burstHelper;
|
|
dram_pkt->burstHelper = NULL;
|
|
}
|
|
} else {
|
|
// it is not a split packet
|
|
accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
|
|
}
|
|
|
|
delete respQueue.front();
|
|
respQueue.pop_front();
|
|
|
|
if (!respQueue.empty()) {
|
|
assert(respQueue.front()->readyTime >= curTick());
|
|
assert(!respondEvent.scheduled());
|
|
schedule(respondEvent, respQueue.front()->readyTime);
|
|
} else {
|
|
// if there is nothing left in any queue, signal a drain
|
|
if (writeQueue.empty() && readQueue.empty() &&
|
|
drainManager) {
|
|
drainManager->signalDrainDone();
|
|
drainManager = NULL;
|
|
}
|
|
}
|
|
|
|
// We have made a location in the queue available at this point,
|
|
// so if there is a read that was forced to wait, retry now
|
|
if (retryRdReq) {
|
|
retryRdReq = false;
|
|
port.sendRetry();
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue)
|
|
{
|
|
// This method does the arbitration between requests. The chosen
|
|
// packet is simply moved to the head of the queue. The other
|
|
// methods know that this is the place to look. For example, with
|
|
// FCFS, this method does nothing
|
|
assert(!queue.empty());
|
|
|
|
if (queue.size() == 1) {
|
|
DPRINTF(DRAM, "Single request, nothing to do\n");
|
|
return;
|
|
}
|
|
|
|
if (memSchedPolicy == Enums::fcfs) {
|
|
// Do nothing, since the correct request is already head
|
|
} else if (memSchedPolicy == Enums::frfcfs) {
|
|
reorderQueue(queue);
|
|
} else
|
|
panic("No scheduling policy chosen\n");
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue)
|
|
{
|
|
// Only determine this when needed
|
|
uint64_t earliest_banks = 0;
|
|
|
|
// Search for row hits first, if no row hit is found then schedule the
|
|
// packet to one of the earliest banks available
|
|
bool found_earliest_pkt = false;
|
|
auto selected_pkt_it = queue.begin();
|
|
|
|
for (auto i = queue.begin(); i != queue.end() ; ++i) {
|
|
DRAMPacket* dram_pkt = *i;
|
|
const Bank& bank = dram_pkt->bankRef;
|
|
// Check if it is a row hit
|
|
if (bank.openRow == dram_pkt->row) {
|
|
DPRINTF(DRAM, "Row buffer hit\n");
|
|
selected_pkt_it = i;
|
|
break;
|
|
} else if (!found_earliest_pkt) {
|
|
// No row hit, go for first ready
|
|
if (earliest_banks == 0)
|
|
earliest_banks = minBankFreeAt(queue);
|
|
|
|
// Bank is ready or is the first available bank
|
|
if (bank.freeAt <= curTick() ||
|
|
bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) {
|
|
// Remember the packet to be scheduled to one of the earliest
|
|
// banks available
|
|
selected_pkt_it = i;
|
|
found_earliest_pkt = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
DRAMPacket* selected_pkt = *selected_pkt_it;
|
|
queue.erase(selected_pkt_it);
|
|
queue.push_front(selected_pkt);
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
|
|
{
|
|
DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
// do the actual memory access which also turns the packet into a
|
|
// response
|
|
access(pkt);
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
if (needsResponse) {
|
|
// access already turned the packet into a response
|
|
assert(pkt->isResponse());
|
|
|
|
// @todo someone should pay for this
|
|
pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
|
|
|
|
// queue the packet in the response queue to be sent out after
|
|
// the static latency has passed
|
|
port.schedTimingResp(pkt, curTick() + static_latency);
|
|
} else {
|
|
// @todo the packet is going to be deleted, and the DRAMPacket
|
|
// is still having a pointer to it
|
|
pendingDelete.push_back(pkt);
|
|
}
|
|
|
|
DPRINTF(DRAM, "Done\n");
|
|
|
|
return;
|
|
}
|
|
|
|
pair<Tick, Tick>
|
|
DRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
|
|
{
|
|
// If a request reaches a bank at tick 'inTime', how much time
|
|
// *after* that does it take to finish the request, depending
|
|
// on bank status and page open policy. Note that this method
|
|
// considers only the time taken for the actual read or write
|
|
// to complete, NOT any additional time thereafter for tRAS or
|
|
// tRP.
|
|
Tick accLat = 0;
|
|
Tick bankLat = 0;
|
|
rowHitFlag = false;
|
|
Tick potentialActTick;
|
|
|
|
const Bank& bank = dram_pkt->bankRef;
|
|
// open-page policy or close_adaptive policy
|
|
if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive ||
|
|
pageMgmt == Enums::close_adaptive) {
|
|
if (bank.openRow == dram_pkt->row) {
|
|
// When we have a row-buffer hit,
|
|
// we don't care about tRAS having expired or not,
|
|
// but do care about bank being free for access
|
|
rowHitFlag = true;
|
|
|
|
// When a series of requests arrive to the same row,
|
|
// DDR systems are capable of streaming data continuously
|
|
// at maximum bandwidth (subject to tCCD). Here, we approximate
|
|
// this condition, and assume that if whenever a bank is already
|
|
// busy and a new request comes in, it can be completed with no
|
|
// penalty beyond waiting for the existing read to complete.
|
|
if (bank.freeAt > inTime) {
|
|
accLat += bank.freeAt - inTime;
|
|
bankLat += 0;
|
|
} else {
|
|
// CAS latency only
|
|
accLat += tCL;
|
|
bankLat += tCL;
|
|
}
|
|
|
|
} else {
|
|
// Row-buffer miss, need to close existing row
|
|
// once tRAS has expired, then open the new one,
|
|
// then add cas latency.
|
|
Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt);
|
|
|
|
if (freeTime > inTime)
|
|
accLat += freeTime - inTime;
|
|
|
|
// If the there is no open row (open adaptive), then there
|
|
// is no precharge delay, otherwise go with tRP
|
|
Tick precharge_delay = bank.openRow == Bank::NO_ROW ? 0 : tRP;
|
|
|
|
//The bank is free, and you may be able to activate
|
|
potentialActTick = inTime + accLat + precharge_delay;
|
|
if (potentialActTick < bank.actAllowedAt)
|
|
accLat += bank.actAllowedAt - potentialActTick;
|
|
|
|
accLat += precharge_delay + tRCD + tCL;
|
|
bankLat += precharge_delay + tRCD + tCL;
|
|
}
|
|
} else if (pageMgmt == Enums::close) {
|
|
// With a close page policy, no notion of
|
|
// bank.tRASDoneAt
|
|
if (bank.freeAt > inTime)
|
|
accLat += bank.freeAt - inTime;
|
|
|
|
//The bank is free, and you may be able to activate
|
|
potentialActTick = inTime + accLat;
|
|
if (potentialActTick < bank.actAllowedAt)
|
|
accLat += bank.actAllowedAt - potentialActTick;
|
|
|
|
// page already closed, simply open the row, and
|
|
// add cas latency
|
|
accLat += tRCD + tCL;
|
|
bankLat += tRCD + tCL;
|
|
} else
|
|
panic("No page management policy chosen\n");
|
|
|
|
DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n",
|
|
bankLat, accLat);
|
|
|
|
return make_pair(bankLat, accLat);
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
|
|
uint16_t row)
|
|
{
|
|
assert(0 <= rank && rank < ranksPerChannel);
|
|
assert(actTicks[rank].size() == activationLimit);
|
|
|
|
DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
|
|
|
|
// idleStartTick is the tick when all the banks were
|
|
// precharged. Thus, the difference between act_tick and
|
|
// idleStartTick gives the time for which the DRAM is in an idle
|
|
// state with all banks precharged. Note that we may end up
|
|
// "changing history" by scheduling an activation before an
|
|
// already scheduled precharge, effectively canceling it out.
|
|
if (numBanksActive == 0 && act_tick > idleStartTick) {
|
|
prechargeAllTime += act_tick - idleStartTick;
|
|
}
|
|
|
|
// update the open row
|
|
assert(banks[rank][bank].openRow == Bank::NO_ROW);
|
|
banks[rank][bank].openRow = row;
|
|
|
|
// start counting anew, this covers both the case when we
|
|
// auto-precharged, and when this access is forced to
|
|
// precharge
|
|
banks[rank][bank].bytesAccessed = 0;
|
|
banks[rank][bank].rowAccesses = 0;
|
|
|
|
++numBanksActive;
|
|
assert(numBanksActive <= banksPerRank * ranksPerChannel);
|
|
|
|
DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n",
|
|
act_tick, numBanksActive);
|
|
|
|
// start by enforcing tRRD
|
|
for(int i = 0; i < banksPerRank; i++) {
|
|
// next activate must not happen before tRRD
|
|
banks[rank][i].actAllowedAt = act_tick + tRRD;
|
|
}
|
|
// tRC should be added to activation tick of the bank currently accessed,
|
|
// where tRC = tRAS + tRP, this is just for a check as actAllowedAt for same
|
|
// bank is already captured by bank.freeAt and bank.tRASDoneAt
|
|
banks[rank][bank].actAllowedAt = act_tick + tRAS + tRP;
|
|
|
|
// next, we deal with tXAW, if the activation limit is disabled
|
|
// then we are done
|
|
if (actTicks[rank].empty())
|
|
return;
|
|
|
|
// sanity check
|
|
if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
|
|
// @todo For now, stick with a warning
|
|
warn("Got %d activates in window %d (%d - %d) which is smaller "
|
|
"than %d\n", activationLimit, act_tick - actTicks[rank].back(),
|
|
act_tick, actTicks[rank].back(), tXAW);
|
|
}
|
|
|
|
// shift the times used for the book keeping, the last element
|
|
// (highest index) is the oldest one and hence the lowest value
|
|
actTicks[rank].pop_back();
|
|
|
|
// record an new activation (in the future)
|
|
actTicks[rank].push_front(act_tick);
|
|
|
|
// cannot activate more than X times in time window tXAW, push the
|
|
// next one (the X + 1'st activate) to be tXAW away from the
|
|
// oldest in our window of X
|
|
if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
|
|
DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier "
|
|
"than %d\n", activationLimit, actTicks[rank].back() + tXAW);
|
|
for(int j = 0; j < banksPerRank; j++)
|
|
// next activate must not happen before end of window
|
|
banks[rank][j].actAllowedAt = actTicks[rank].back() + tXAW;
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::prechargeBank(Bank& bank, Tick free_at)
|
|
{
|
|
// make sure the bank has an open row
|
|
assert(bank.openRow != Bank::NO_ROW);
|
|
|
|
// sample the bytes per activate here since we are closing
|
|
// the page
|
|
bytesPerActivate.sample(bank.bytesAccessed);
|
|
|
|
bank.openRow = Bank::NO_ROW;
|
|
|
|
bank.freeAt = free_at;
|
|
|
|
assert(numBanksActive != 0);
|
|
--numBanksActive;
|
|
|
|
DPRINTF(DRAM, "Precharged bank, done at tick %lld, now got %d active\n",
|
|
bank.freeAt, numBanksActive);
|
|
|
|
// if we reached zero, then special conditions apply as we track
|
|
// if all banks are precharged for the power models
|
|
if (numBanksActive == 0) {
|
|
idleStartTick = std::max(idleStartTick, bank.freeAt);
|
|
DPRINTF(DRAM, "All banks precharged at tick: %ld\n",
|
|
idleStartTick);
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
|
|
{
|
|
|
|
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
|
|
dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
|
|
|
|
// estimate the bank and access latency
|
|
pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick());
|
|
Tick bankLat = lat.first;
|
|
Tick accessLat = lat.second;
|
|
Tick actTick;
|
|
|
|
// This request was woken up at this time based on a prior call
|
|
// to estimateLatency(). However, between then and now, both the
|
|
// accessLatency and/or busBusyUntil may have changed. We need
|
|
// to correct for that.
|
|
|
|
Tick addDelay = (curTick() + accessLat < busBusyUntil) ?
|
|
busBusyUntil - (curTick() + accessLat) : 0;
|
|
|
|
Bank& bank = dram_pkt->bankRef;
|
|
|
|
// Update bank state
|
|
if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive ||
|
|
pageMgmt == Enums::close_adaptive) {
|
|
|
|
if (rowHitFlag) {
|
|
bank.freeAt = curTick() + addDelay + accessLat;
|
|
} else {
|
|
// If there is a page open, precharge it.
|
|
if (bank.openRow != Bank::NO_ROW) {
|
|
prechargeBank(bank, std::max(std::max(bank.freeAt,
|
|
bank.tRASDoneAt),
|
|
curTick()) + tRP);
|
|
}
|
|
|
|
// Any precharge is already part of the latency
|
|
// estimation, so update the bank free time
|
|
bank.freeAt = curTick() + addDelay + accessLat;
|
|
|
|
// any waiting for banks account for in freeAt
|
|
actTick = bank.freeAt - tCL - tRCD;
|
|
|
|
// If you activated a new row do to this access, the next access
|
|
// will have to respect tRAS for this bank
|
|
bank.tRASDoneAt = actTick + tRAS;
|
|
|
|
recordActivate(actTick, dram_pkt->rank, dram_pkt->bank,
|
|
dram_pkt->row);
|
|
}
|
|
|
|
// increment the bytes accessed and the accesses per row
|
|
bank.bytesAccessed += burstSize;
|
|
++bank.rowAccesses;
|
|
|
|
// if we reached the max, then issue with an auto-precharge
|
|
bool auto_precharge = bank.rowAccesses == maxAccessesPerRow;
|
|
|
|
// if we did not hit the limit, we might still want to
|
|
// auto-precharge
|
|
if (!auto_precharge &&
|
|
(pageMgmt == Enums::open_adaptive ||
|
|
pageMgmt == Enums::close_adaptive)) {
|
|
// a twist on the open and close page policies:
|
|
// 1) open_adaptive page policy does not blindly keep the
|
|
// page open, but close it if there are no row hits, and there
|
|
// are bank conflicts in the queue
|
|
// 2) close_adaptive page policy does not blindly close the
|
|
// page, but closes it only if there are no row hits in the queue.
|
|
// In this case, only force an auto precharge when there
|
|
// are no same page hits in the queue
|
|
bool got_more_hits = false;
|
|
bool got_bank_conflict = false;
|
|
|
|
// either look at the read queue or write queue
|
|
const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
|
|
writeQueue;
|
|
auto p = queue.begin();
|
|
// make sure we are not considering the packet that we are
|
|
// currently dealing with (which is the head of the queue)
|
|
++p;
|
|
|
|
// keep on looking until we have found required condition or
|
|
// reached the end
|
|
while (!(got_more_hits &&
|
|
(got_bank_conflict || pageMgmt == Enums::close_adaptive)) &&
|
|
p != queue.end()) {
|
|
bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
|
|
(dram_pkt->bank == (*p)->bank);
|
|
bool same_row = dram_pkt->row == (*p)->row;
|
|
got_more_hits |= same_rank_bank && same_row;
|
|
got_bank_conflict |= same_rank_bank && !same_row;
|
|
++p;
|
|
}
|
|
|
|
// auto pre-charge when either
|
|
// 1) open_adaptive policy, we have not got any more hits, and
|
|
// have a bank conflict
|
|
// 2) close_adaptive policy and we have not got any more hits
|
|
auto_precharge = !got_more_hits &&
|
|
(got_bank_conflict || pageMgmt == Enums::close_adaptive);
|
|
}
|
|
|
|
// if this access should use auto-precharge, then we are
|
|
// closing the row
|
|
if (auto_precharge) {
|
|
prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP);
|
|
|
|
DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
|
|
}
|
|
|
|
DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt);
|
|
} else if (pageMgmt == Enums::close) {
|
|
actTick = curTick() + addDelay + accessLat - tRCD - tCL;
|
|
recordActivate(actTick, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
|
|
|
|
bank.freeAt = actTick + tRCD + tCL;
|
|
bank.tRASDoneAt = actTick + tRAS;
|
|
|
|
// sample the relevant values when precharging
|
|
bank.bytesAccessed = burstSize;
|
|
bank.rowAccesses = 1;
|
|
|
|
prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP);
|
|
DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt);
|
|
} else
|
|
panic("No page management policy chosen\n");
|
|
|
|
// Update request parameters
|
|
dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST;
|
|
|
|
|
|
DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \
|
|
"readytime is %lld busbusyuntil is %lld. " \
|
|
"Scheduling at readyTime\n", dram_pkt->addr,
|
|
curTick(), accessLat, dram_pkt->readyTime, busBusyUntil);
|
|
|
|
// Make sure requests are not overlapping on the databus
|
|
assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
|
|
|
|
// Update bus state
|
|
busBusyUntil = dram_pkt->readyTime;
|
|
|
|
DPRINTF(DRAM,"Access time is %lld\n",
|
|
dram_pkt->readyTime - dram_pkt->entryTime);
|
|
|
|
// Update the minimum timing between the requests, this is a
|
|
// conservative estimate of when we have to schedule the next
|
|
// request to not introduce any unecessary bubbles. In most cases
|
|
// we will wake up sooner than we have to.
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
|
|
|
// Update the stats and schedule the next request
|
|
if (dram_pkt->isRead) {
|
|
++readsThisTime;
|
|
if (rowHitFlag)
|
|
readRowHits++;
|
|
bytesReadDRAM += burstSize;
|
|
perBankRdBursts[dram_pkt->bankId]++;
|
|
|
|
// Update latency stats
|
|
totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
|
|
totBankLat += bankLat;
|
|
totBusLat += tBURST;
|
|
totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat -
|
|
tBURST;
|
|
} else {
|
|
++writesThisTime;
|
|
if (rowHitFlag)
|
|
writeRowHits++;
|
|
bytesWritten += burstSize;
|
|
perBankWrBursts[dram_pkt->bankId]++;
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::moveToRespQ()
|
|
{
|
|
// Remove from read queue
|
|
DRAMPacket* dram_pkt = readQueue.front();
|
|
readQueue.pop_front();
|
|
|
|
// sanity check
|
|
assert(dram_pkt->size <= burstSize);
|
|
|
|
// Insert into response queue sorted by readyTime
|
|
// It will be sent back to the requestor at its
|
|
// readyTime
|
|
if (respQueue.empty()) {
|
|
respQueue.push_front(dram_pkt);
|
|
assert(!respondEvent.scheduled());
|
|
assert(dram_pkt->readyTime >= curTick());
|
|
schedule(respondEvent, dram_pkt->readyTime);
|
|
} else {
|
|
bool done = false;
|
|
auto i = respQueue.begin();
|
|
while (!done && i != respQueue.end()) {
|
|
if ((*i)->readyTime > dram_pkt->readyTime) {
|
|
respQueue.insert(i, dram_pkt);
|
|
done = true;
|
|
}
|
|
++i;
|
|
}
|
|
|
|
if (!done)
|
|
respQueue.push_back(dram_pkt);
|
|
|
|
assert(respondEvent.scheduled());
|
|
|
|
if (respQueue.front()->readyTime < respondEvent.when()) {
|
|
assert(respQueue.front()->readyTime >= curTick());
|
|
reschedule(respondEvent, respQueue.front()->readyTime);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::processNextReqEvent()
|
|
{
|
|
if (busState == READ_TO_WRITE) {
|
|
DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
|
|
"waiting\n", readsThisTime, readQueue.size());
|
|
|
|
// sample and reset the read-related stats as we are now
|
|
// transitioning to writes, and all reads are done
|
|
rdPerTurnAround.sample(readsThisTime);
|
|
readsThisTime = 0;
|
|
|
|
// now proceed to do the actual writes
|
|
busState = WRITE;
|
|
} else if (busState == WRITE_TO_READ) {
|
|
DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
|
|
"waiting\n", writesThisTime, writeQueue.size());
|
|
|
|
wrPerTurnAround.sample(writesThisTime);
|
|
writesThisTime = 0;
|
|
|
|
busState = READ;
|
|
}
|
|
|
|
if (refreshState != REF_IDLE) {
|
|
// if a refresh waiting for this event loop to finish, then hand
|
|
// over now, and do not schedule a new nextReqEvent
|
|
if (refreshState == REF_DRAIN) {
|
|
DPRINTF(DRAM, "Refresh drain done, now precharging\n");
|
|
|
|
refreshState = REF_PRE;
|
|
|
|
// hand control back to the refresh event loop
|
|
schedule(refreshEvent, curTick());
|
|
}
|
|
|
|
// let the refresh finish before issuing any further requests
|
|
return;
|
|
}
|
|
|
|
// when we get here it is either a read or a write
|
|
if (busState == READ) {
|
|
|
|
// track if we should switch or not
|
|
bool switch_to_writes = false;
|
|
|
|
if (readQueue.empty()) {
|
|
// In the case there is no read request to go next,
|
|
// trigger writes if we have passed the low threshold (or
|
|
// if we are draining)
|
|
if (!writeQueue.empty() &&
|
|
(drainManager || writeQueue.size() > writeLowThreshold)) {
|
|
|
|
switch_to_writes = true;
|
|
} else {
|
|
// check if we are drained
|
|
if (respQueue.empty () && drainManager) {
|
|
drainManager->signalDrainDone();
|
|
drainManager = NULL;
|
|
}
|
|
|
|
// nothing to do, not even any point in scheduling an
|
|
// event for the next request
|
|
return;
|
|
}
|
|
} else {
|
|
// Figure out which read request goes next, and move it to the
|
|
// front of the read queue
|
|
chooseNext(readQueue);
|
|
|
|
doDRAMAccess(readQueue.front());
|
|
|
|
// At this point we're done dealing with the request
|
|
// It will be moved to a separate response queue with a
|
|
// correct readyTime, and eventually be sent back at that
|
|
// time
|
|
moveToRespQ();
|
|
|
|
// we have so many writes that we have to transition
|
|
if (writeQueue.size() > writeHighThreshold) {
|
|
switch_to_writes = true;
|
|
}
|
|
}
|
|
|
|
// switching to writes, either because the read queue is empty
|
|
// and the writes have passed the low threshold (or we are
|
|
// draining), or because the writes hit the hight threshold
|
|
if (switch_to_writes) {
|
|
// transition to writing
|
|
busState = READ_TO_WRITE;
|
|
|
|
// add a bubble to the data bus, as defined by the
|
|
// tRTW parameter
|
|
busBusyUntil += tRTW;
|
|
|
|
// update the minimum timing between the requests,
|
|
// this shifts us back in time far enough to do any
|
|
// bank preparation
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
|
}
|
|
} else {
|
|
chooseNext(writeQueue);
|
|
DRAMPacket* dram_pkt = writeQueue.front();
|
|
// sanity check
|
|
assert(dram_pkt->size <= burstSize);
|
|
doDRAMAccess(dram_pkt);
|
|
|
|
writeQueue.pop_front();
|
|
delete dram_pkt;
|
|
|
|
// If we emptied the write queue, or got sufficiently below the
|
|
// threshold (using the minWritesPerSwitch as the hysteresis) and
|
|
// are not draining, or we have reads waiting and have done enough
|
|
// writes, then switch to reads.
|
|
if (writeQueue.empty() ||
|
|
(writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
|
|
!drainManager) ||
|
|
(!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
|
|
// turn the bus back around for reads again
|
|
busState = WRITE_TO_READ;
|
|
|
|
// note that the we switch back to reads also in the idle
|
|
// case, which eventually will check for any draining and
|
|
// also pause any further scheduling if there is really
|
|
// nothing to do
|
|
|
|
// here we get a bit creative and shift the bus busy time not
|
|
// just the tWTR, but also a CAS latency to capture the fact
|
|
// that we are allowed to prepare a new bank, but not issue a
|
|
// read command until after tWTR, in essence we capture a
|
|
// bubble on the data bus that is tWTR + tCL
|
|
busBusyUntil += tWTR + tCL;
|
|
|
|
// update the minimum timing between the requests, this shifts
|
|
// us back in time far enough to do any bank preparation
|
|
nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
|
|
}
|
|
}
|
|
|
|
schedule(nextReqEvent, std::max(nextReqTime, curTick()));
|
|
|
|
// If there is space available and we have writes waiting then let
|
|
// them retry. This is done here to ensure that the retry does not
|
|
// cause a nextReqEvent to be scheduled before we do so as part of
|
|
// the next request processing
|
|
if (retryWrReq && writeQueue.size() < writeBufferSize) {
|
|
retryWrReq = false;
|
|
port.sendRetry();
|
|
}
|
|
}
|
|
|
|
uint64_t
|
|
DRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const
|
|
{
|
|
uint64_t bank_mask = 0;
|
|
Tick freeAt = MaxTick;
|
|
|
|
// detemrine if we have queued transactions targetting the
|
|
// bank in question
|
|
vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
|
|
for (auto p = queue.begin(); p != queue.end(); ++p) {
|
|
got_waiting[(*p)->bankId] = true;
|
|
}
|
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
for (int j = 0; j < banksPerRank; j++) {
|
|
// if we have waiting requests for the bank, and it is
|
|
// amongst the first available, update the mask
|
|
if (got_waiting[i * banksPerRank + j] &&
|
|
banks[i][j].freeAt <= freeAt) {
|
|
// reset bank mask if new minimum is found
|
|
if (banks[i][j].freeAt < freeAt)
|
|
bank_mask = 0;
|
|
// set the bit corresponding to the available bank
|
|
uint8_t bit_index = i * ranksPerChannel + j;
|
|
replaceBits(bank_mask, bit_index, bit_index, 1);
|
|
freeAt = banks[i][j].freeAt;
|
|
}
|
|
}
|
|
}
|
|
return bank_mask;
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::processRefreshEvent()
|
|
{
|
|
// when first preparing the refresh, remember when it was due
|
|
if (refreshState == REF_IDLE) {
|
|
// remember when the refresh is due
|
|
refreshDueAt = curTick();
|
|
|
|
// proceed to drain
|
|
refreshState = REF_DRAIN;
|
|
|
|
DPRINTF(DRAM, "Refresh due\n");
|
|
}
|
|
|
|
// let any scheduled read or write go ahead, after which it will
|
|
// hand control back to this event loop
|
|
if (refreshState == REF_DRAIN) {
|
|
if (nextReqEvent.scheduled()) {
|
|
// hand control over to the request loop until it is
|
|
// evaluated next
|
|
DPRINTF(DRAM, "Refresh awaiting draining\n");
|
|
|
|
return;
|
|
} else {
|
|
refreshState = REF_PRE;
|
|
}
|
|
}
|
|
|
|
// at this point, ensure that all banks are precharged
|
|
if (refreshState == REF_PRE) {
|
|
DPRINTF(DRAM, "Precharging all\n");
|
|
|
|
// precharge any active bank
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
for (int j = 0; j < banksPerRank; j++) {
|
|
if (banks[i][j].openRow != Bank::NO_ROW) {
|
|
// respect both causality and any existing bank
|
|
// constraints
|
|
Tick free_at = std::max(std::max(banks[i][j].freeAt,
|
|
banks[i][j].tRASDoneAt),
|
|
curTick()) + tRP;
|
|
|
|
prechargeBank(banks[i][j], free_at);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (numBanksActive != 0)
|
|
panic("Refresh scheduled with %d active banks\n", numBanksActive);
|
|
|
|
// advance the state
|
|
refreshState = REF_RUN;
|
|
|
|
// call ourselves in the future
|
|
schedule(refreshEvent, std::max(curTick(), idleStartTick));
|
|
return;
|
|
}
|
|
|
|
// last but not least we perform the actual refresh
|
|
if (refreshState == REF_RUN) {
|
|
// should never get here with any banks active
|
|
assert(numBanksActive == 0);
|
|
|
|
Tick banksFree = curTick() + tRFC;
|
|
|
|
for (int i = 0; i < ranksPerChannel; i++) {
|
|
for (int j = 0; j < banksPerRank; j++) {
|
|
banks[i][j].freeAt = banksFree;
|
|
}
|
|
}
|
|
|
|
// make sure we did not wait so long that we cannot make up
|
|
// for it
|
|
if (refreshDueAt + tREFI < banksFree) {
|
|
fatal("Refresh was delayed so long we cannot catch up\n");
|
|
}
|
|
|
|
// compensate for the delay in actually performing the refresh
|
|
// when scheduling the next one
|
|
schedule(refreshEvent, refreshDueAt + tREFI - tRP);
|
|
|
|
// back to business as usual
|
|
refreshState = REF_IDLE;
|
|
|
|
// we are now refreshing until tRFC is done
|
|
idleStartTick = banksFree;
|
|
|
|
// kick the normal request processing loop into action again
|
|
// as early as possible, i.e. when the request is done, the
|
|
// scheduling of this event also prevents any new requests
|
|
// from going ahead before the scheduled point in time
|
|
nextReqTime = banksFree;
|
|
schedule(nextReqEvent, nextReqTime);
|
|
}
|
|
}
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void
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DRAMCtrl::regStats()
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{
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using namespace Stats;
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AbstractMemory::regStats();
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readReqs
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.name(name() + ".readReqs")
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.desc("Number of read requests accepted");
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writeReqs
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.name(name() + ".writeReqs")
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.desc("Number of write requests accepted");
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readBursts
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.name(name() + ".readBursts")
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.desc("Number of DRAM read bursts, "
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"including those serviced by the write queue");
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writeBursts
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.name(name() + ".writeBursts")
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.desc("Number of DRAM write bursts, "
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"including those merged in the write queue");
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servicedByWrQ
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.name(name() + ".servicedByWrQ")
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.desc("Number of DRAM read bursts serviced by the write queue");
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mergedWrBursts
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.name(name() + ".mergedWrBursts")
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.desc("Number of DRAM write bursts merged with an existing one");
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neitherReadNorWrite
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.name(name() + ".neitherReadNorWriteReqs")
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.desc("Number of requests that are neither read nor write");
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perBankRdBursts
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.init(banksPerRank * ranksPerChannel)
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.name(name() + ".perBankRdBursts")
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.desc("Per bank write bursts");
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perBankWrBursts
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.init(banksPerRank * ranksPerChannel)
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.name(name() + ".perBankWrBursts")
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.desc("Per bank write bursts");
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avgRdQLen
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.name(name() + ".avgRdQLen")
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.desc("Average read queue length when enqueuing")
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.precision(2);
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avgWrQLen
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.name(name() + ".avgWrQLen")
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.desc("Average write queue length when enqueuing")
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.precision(2);
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totQLat
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.name(name() + ".totQLat")
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.desc("Total ticks spent queuing");
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totBankLat
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.name(name() + ".totBankLat")
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.desc("Total ticks spent accessing banks");
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totBusLat
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.name(name() + ".totBusLat")
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.desc("Total ticks spent in databus transfers");
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totMemAccLat
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.name(name() + ".totMemAccLat")
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.desc("Total ticks spent from burst creation until serviced "
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"by the DRAM");
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avgQLat
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.name(name() + ".avgQLat")
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.desc("Average queueing delay per DRAM burst")
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.precision(2);
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avgQLat = totQLat / (readBursts - servicedByWrQ);
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avgBankLat
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.name(name() + ".avgBankLat")
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.desc("Average bank access latency per DRAM burst")
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.precision(2);
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avgBankLat = totBankLat / (readBursts - servicedByWrQ);
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avgBusLat
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.name(name() + ".avgBusLat")
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.desc("Average bus latency per DRAM burst")
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.precision(2);
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avgBusLat = totBusLat / (readBursts - servicedByWrQ);
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avgMemAccLat
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.name(name() + ".avgMemAccLat")
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.desc("Average memory access latency per DRAM burst")
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.precision(2);
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avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ);
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numRdRetry
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.name(name() + ".numRdRetry")
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.desc("Number of times read queue was full causing retry");
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numWrRetry
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.name(name() + ".numWrRetry")
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.desc("Number of times write queue was full causing retry");
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readRowHits
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.name(name() + ".readRowHits")
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.desc("Number of row buffer hits during reads");
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writeRowHits
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.name(name() + ".writeRowHits")
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.desc("Number of row buffer hits during writes");
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readRowHitRate
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.name(name() + ".readRowHitRate")
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.desc("Row buffer hit rate for reads")
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.precision(2);
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readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100;
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writeRowHitRate
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.name(name() + ".writeRowHitRate")
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.desc("Row buffer hit rate for writes")
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.precision(2);
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writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100;
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readPktSize
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.init(ceilLog2(burstSize) + 1)
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.name(name() + ".readPktSize")
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.desc("Read request sizes (log2)");
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writePktSize
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.init(ceilLog2(burstSize) + 1)
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.name(name() + ".writePktSize")
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.desc("Write request sizes (log2)");
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rdQLenPdf
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.init(readBufferSize)
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.name(name() + ".rdQLenPdf")
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.desc("What read queue length does an incoming req see");
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wrQLenPdf
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.init(writeBufferSize)
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.name(name() + ".wrQLenPdf")
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.desc("What write queue length does an incoming req see");
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bytesPerActivate
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.init(maxAccessesPerRow)
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.name(name() + ".bytesPerActivate")
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.desc("Bytes accessed per row activation")
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.flags(nozero);
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rdPerTurnAround
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.init(readBufferSize)
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.name(name() + ".rdPerTurnAround")
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.desc("Reads before turning the bus around for writes")
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.flags(nozero);
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wrPerTurnAround
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.init(writeBufferSize)
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.name(name() + ".wrPerTurnAround")
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.desc("Writes before turning the bus around for reads")
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.flags(nozero);
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bytesReadDRAM
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.name(name() + ".bytesReadDRAM")
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.desc("Total number of bytes read from DRAM");
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bytesReadWrQ
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.name(name() + ".bytesReadWrQ")
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.desc("Total number of bytes read from write queue");
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bytesWritten
|
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.name(name() + ".bytesWritten")
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.desc("Total number of bytes written to DRAM");
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bytesReadSys
|
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.name(name() + ".bytesReadSys")
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.desc("Total read bytes from the system interface side");
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bytesWrittenSys
|
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.name(name() + ".bytesWrittenSys")
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.desc("Total written bytes from the system interface side");
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avgRdBW
|
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.name(name() + ".avgRdBW")
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.desc("Average DRAM read bandwidth in MiByte/s")
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.precision(2);
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avgRdBW = (bytesReadDRAM / 1000000) / simSeconds;
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avgWrBW
|
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.name(name() + ".avgWrBW")
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.desc("Average achieved write bandwidth in MiByte/s")
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.precision(2);
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avgWrBW = (bytesWritten / 1000000) / simSeconds;
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avgRdBWSys
|
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.name(name() + ".avgRdBWSys")
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.desc("Average system read bandwidth in MiByte/s")
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.precision(2);
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avgRdBWSys = (bytesReadSys / 1000000) / simSeconds;
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avgWrBWSys
|
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.name(name() + ".avgWrBWSys")
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.desc("Average system write bandwidth in MiByte/s")
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.precision(2);
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avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds;
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peakBW
|
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.name(name() + ".peakBW")
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.desc("Theoretical peak bandwidth in MiByte/s")
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.precision(2);
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peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;
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busUtil
|
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.name(name() + ".busUtil")
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.desc("Data bus utilization in percentage")
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.precision(2);
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busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
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totGap
|
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.name(name() + ".totGap")
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.desc("Total gap between requests");
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avgGap
|
|
.name(name() + ".avgGap")
|
|
.desc("Average gap between requests")
|
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.precision(2);
|
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|
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avgGap = totGap / (readReqs + writeReqs);
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|
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// Stats for DRAM Power calculation based on Micron datasheet
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busUtilRead
|
|
.name(name() + ".busUtilRead")
|
|
.desc("Data bus utilization in percentage for reads")
|
|
.precision(2);
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busUtilRead = avgRdBW / peakBW * 100;
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|
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busUtilWrite
|
|
.name(name() + ".busUtilWrite")
|
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.desc("Data bus utilization in percentage for writes")
|
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.precision(2);
|
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|
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busUtilWrite = avgWrBW / peakBW * 100;
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pageHitRate
|
|
.name(name() + ".pageHitRate")
|
|
.desc("Row buffer hit rate, read and write combined")
|
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.precision(2);
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|
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pageHitRate = (writeRowHits + readRowHits) /
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(writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
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|
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prechargeAllPercent
|
|
.name(name() + ".prechargeAllPercent")
|
|
.desc("Percentage of time for which DRAM has all the banks in "
|
|
"precharge state")
|
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.precision(2);
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|
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prechargeAllPercent = prechargeAllTime / simTicks * 100;
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}
|
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|
|
void
|
|
DRAMCtrl::recvFunctional(PacketPtr pkt)
|
|
{
|
|
// rely on the abstract memory
|
|
functionalAccess(pkt);
|
|
}
|
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|
|
BaseSlavePort&
|
|
DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
|
|
{
|
|
if (if_name != "port") {
|
|
return MemObject::getSlavePort(if_name, idx);
|
|
} else {
|
|
return port;
|
|
}
|
|
}
|
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|
|
unsigned int
|
|
DRAMCtrl::drain(DrainManager *dm)
|
|
{
|
|
unsigned int count = port.drain(dm);
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|
|
|
// if there is anything in any of our internal queues, keep track
|
|
// of that as well
|
|
if (!(writeQueue.empty() && readQueue.empty() &&
|
|
respQueue.empty())) {
|
|
DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
|
|
" resp: %d\n", writeQueue.size(), readQueue.size(),
|
|
respQueue.size());
|
|
++count;
|
|
drainManager = dm;
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|
|
// the only part that is not drained automatically over time
|
|
// is the write queue, thus kick things into action if needed
|
|
if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
|
|
schedule(nextReqEvent, curTick());
|
|
}
|
|
}
|
|
|
|
if (count)
|
|
setDrainState(Drainable::Draining);
|
|
else
|
|
setDrainState(Drainable::Drained);
|
|
return count;
|
|
}
|
|
|
|
DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
|
|
: QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
|
|
memory(_memory)
|
|
{ }
|
|
|
|
AddrRangeList
|
|
DRAMCtrl::MemoryPort::getAddrRanges() const
|
|
{
|
|
AddrRangeList ranges;
|
|
ranges.push_back(memory.getAddrRange());
|
|
return ranges;
|
|
}
|
|
|
|
void
|
|
DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
|
|
{
|
|
pkt->pushLabel(memory.name());
|
|
|
|
if (!queue.checkFunctional(pkt)) {
|
|
// Default implementation of SimpleTimingPort::recvFunctional()
|
|
// calls recvAtomic() and throws away the latency; we can save a
|
|
// little here by just not calculating the latency.
|
|
memory.recvFunctional(pkt);
|
|
}
|
|
|
|
pkt->popLabel();
|
|
}
|
|
|
|
Tick
|
|
DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
|
|
{
|
|
return memory.recvAtomic(pkt);
|
|
}
|
|
|
|
bool
|
|
DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
|
|
{
|
|
// pass it to the memory controller
|
|
return memory.recvTimingReq(pkt);
|
|
}
|
|
|
|
DRAMCtrl*
|
|
DRAMCtrlParams::create()
|
|
{
|
|
return new DRAMCtrl(this);
|
|
}
|