Giacomo Travaglini 058dd7e195 configs, tests: Amend stdlib configs to use WalkCache hierarchy ...

As X86 and RISCV are relying on a Table Walker cache, we
change their stdlib configs to use the newly defined

PrivateL1PrivateL2WalkCacheHierarchy

Change-Id: I63c3f70a9daa3b2c7a8306e51af8065bf1bea92b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-03-18 09:42:05 +00:00

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checkpoints

configs, tests: Amend stdlib configs to use WalkCache hierarchy

2024-03-18 09:42:05 +00:00

dramsys

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looppoints

configs, tests: Amend stdlib configs to use WalkCache hierarchy

2024-03-18 09:42:05 +00:00

arm-hello.py

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arm-ubuntu-run-with-kvm.py

arm,stdlib: added kvm support to the ARM board (#725)

2024-01-31 10:17:58 -08:00

arm-ubuntu-run.py

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memory_traffic.py

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power-hello.py

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riscv-fs.py

configs, tests: Amend stdlib configs to use WalkCache hierarchy

2024-03-18 09:42:05 +00:00

riscv-ubuntu-run.py

configs, tests: Amend stdlib configs to use WalkCache hierarchy

2024-03-18 09:42:05 +00:00

riscvmatched-fs.py

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riscvmatched-hello.py

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riscvmatched-microbenchmark-suite.py

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x86-gapbs-benchmarks.py

misc: update gapbs example to use suites (#607)

2023-12-03 13:21:37 -08:00

x86-npb-benchmarks.py

misc: update x86-npb-benchmarks.py to use suites (#587)

2023-12-03 13:23:46 -08:00

x86-parsec-benchmarks.py

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x86-spec-cpu2006-benchmarks.py

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x86-spec-cpu2017-benchmarks.py

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x86-ubuntu-run-with-kvm-no-perf.py

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x86-ubuntu-run-with-kvm.py

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x86-ubuntu-run.py

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