b98b648797
When a message triggers a transition that has actions which allocate TBEs, the generated code automatically includes a check for the TBETable size before executing any action. If the table is full, the transition returns TransitionResult_ResourceStall and no more messages from the buffer are handled (until the next cycle). This behavior may lead to deadlocks in the MOESI_CMP_directory protocol since events triggered by the response queue may allocate TBEs (e.g. L2 replacements triggered by the response queue). If the table is full, the queue is stalled preventing other responses from freeing TBEs. This patch fixes this by handling WRITEBACK_DIRTY_DATA/CLEAN_DATA messages as requests and WB_ACK/WB_NACK as responses. All controllers are changed to work with the new types. With this fix, responses are always handled first in all controllers, and no response triggers TBE allocations. Change-Id: I377c0ec4f06d528e9f0541daf3dcc621184f2524 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18408 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
153 lines
6.3 KiB
Plaintext
153 lines
6.3 KiB
Plaintext
/*
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* Copyright (c) 2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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*/
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// CoherenceRequestType
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enumeration(CoherenceRequestType, desc="...") {
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GETX, desc="Get eXclusive";
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GETS, desc="Get Shared";
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PUTX, desc="Put eXclusive";
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PUTO, desc="Put Owned";
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PUTO_SHARERS, desc="Put Owned, but sharers exist so don't remove from sharers list";
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PUTS, desc="Put Shared";
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INV, desc="Invalidation";
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WRITEBACK_CLEAN_DATA, desc="Clean writeback (contains data)";
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WRITEBACK_CLEAN_ACK, desc="Clean writeback (contains no data)";
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WRITEBACK_DIRTY_DATA, desc="Dirty writeback (contains data)";
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DMA_READ, desc="DMA Read";
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DMA_WRITE, desc="DMA Write";
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}
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// CoherenceResponseType
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enumeration(CoherenceResponseType, desc="...") {
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ACK, desc="ACKnowledgment, responder doesn't have a copy";
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DATA, desc="Data";
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DATA_EXCLUSIVE, desc="Data, no processor has a copy";
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UNBLOCK, desc="Unblock";
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UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
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WB_ACK, desc="Writeback ack";
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WB_ACK_DATA, desc="Writeback ack";
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WB_NACK, desc="Writeback neg. ack";
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DMA_ACK, desc="Ack that a DMA write completed";
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}
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// TriggerType
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enumeration(TriggerType, desc="...") {
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ALL_ACKS, desc="See corresponding event";
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}
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// TriggerMsg
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structure(TriggerMsg, desc="...", interface="Message") {
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Addr addr, desc="Physical address for this request";
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TriggerType Type, desc="Type of trigger";
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bool functionalRead(Packet *pkt) {
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// Trigger message does not hold data
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return false;
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}
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bool functionalWrite(Packet *pkt) {
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// Trigger message does not hold data
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return false;
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}
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}
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// RequestMsg (and also forwarded requests)
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structure(RequestMsg, desc="...", interface="Message") {
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Addr addr, desc="Physical address for this request";
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int Len, desc="Length of Request";
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CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
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MachineID Requestor, desc="Node who initiated the request";
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MachineType RequestorMachine, desc="type of component";
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NetDest Destination, desc="Multicast destination mask";
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DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)";
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int Acks, desc="How many acks to expect";
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MessageSizeType MessageSize, desc="size category of the message";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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bool functionalRead(Packet *pkt) {
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// Read only those messages that contain the data
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if (Type == CoherenceRequestType:DMA_READ ||
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Type == CoherenceRequestType:DMA_WRITE ||
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Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA ||
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Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) {
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return testAndRead(addr, DataBlk, pkt);
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}
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return false;
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}
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bool functionalWrite(Packet *pkt) {
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// No check required since all messages are written
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return testAndWrite(addr, DataBlk, pkt);
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}
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}
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// ResponseMsg (and also unblock requests)
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structure(ResponseMsg, desc="...", interface="Message") {
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Addr addr, desc="Physical address for this request";
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CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
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MachineID Sender, desc="Node who sent the data";
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MachineType SenderMachine, desc="type of component sending msg";
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NetDest Destination, desc="Node to whom the data is sent";
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DataBlock DataBlk, desc="data for the cache line";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int Acks, desc="How many acks to expect";
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MessageSizeType MessageSize, desc="size category of the message";
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bool functionalRead(Packet *pkt) {
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// Read only those messages that contain the data
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if (Type == CoherenceResponseType:DATA ||
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Type == CoherenceResponseType:DATA_EXCLUSIVE) {
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return testAndRead(addr, DataBlk, pkt);
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}
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return false;
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}
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bool functionalWrite(Packet *pkt) {
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// No check required since all messages are written
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return testAndWrite(addr, DataBlk, pkt);
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}
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}
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