b8da9abba7
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
250 lines
11 KiB
Python
250 lines
11 KiB
Python
# Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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from m5.objects.Bridge import Bridge
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from m5.objects.ClockedObject import ClockedObject
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from m5.objects.Device import DmaDevice
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from m5.objects.HSADevice import HSADevice
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from m5.objects.HSADriver import HSADriver
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from m5.objects.LdsState import LdsState
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from m5.objects.Process import EmulatedDriver
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class PrefetchType(Enum): vals = [
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'PF_CU',
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'PF_PHASE',
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'PF_WF',
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'PF_STRIDE',
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'PF_END',
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]
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class PoolManager(SimObject):
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type = 'PoolManager'
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abstract = True
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cxx_header = "gpu-compute/pool_manager.hh"
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min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF')
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pool_size = Param.Int(2048, 'number of vector registers per SIMD')
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# The simple pool manage only allows one workgroup to
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# be executing on a CU at any given time.
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class SimplePoolManager(PoolManager):
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type = 'SimplePoolManager'
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cxx_class = 'SimplePoolManager'
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cxx_header = "gpu-compute/simple_pool_manager.hh"
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class RegisterFile(SimObject):
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type = 'RegisterFile'
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cxx_class = 'RegisterFile'
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cxx_header = 'gpu-compute/register_file.hh'
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simd_id = Param.Int(-1, 'SIMD ID associated with this Register File')
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num_regs = Param.Int(2048, 'number of registers in this RF')
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wf_size = Param.Int(64, 'Wavefront size (in work items)')
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class ScalarRegisterFile(RegisterFile):
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type = 'ScalarRegisterFile'
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cxx_class = 'ScalarRegisterFile'
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cxx_header = 'gpu-compute/scalar_register_file.hh'
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class VectorRegisterFile(RegisterFile):
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type = 'VectorRegisterFile'
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cxx_class = 'VectorRegisterFile'
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cxx_header = 'gpu-compute/vector_register_file.hh'
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class RegisterManager(SimObject):
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type = 'RegisterManager'
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cxx_class = 'RegisterManager'
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cxx_header = 'gpu-compute/register_manager.hh'
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policy = Param.String("static", "Register Manager Policy")
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vrf_pool_managers = VectorParam.PoolManager('VRF Pool Managers')
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srf_pool_managers = VectorParam.PoolManager('SRF Pool Managers')
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class Wavefront(SimObject):
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type = 'Wavefront'
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cxx_class = 'Wavefront'
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cxx_header = 'gpu-compute/wavefront.hh'
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simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)')
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wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
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wf_size = Param.Int(64, 'Wavefront size (in work items)')
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max_ib_size = Param.Int(13, 'Maximum size (in number of insts) of the '
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'instruction buffer (IB).')
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# Most of the default values here are obtained from the
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# AMD Graphics Core Next (GCN) Architecture whitepaper.
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class ComputeUnit(ClockedObject):
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type = 'ComputeUnit'
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cxx_class = 'ComputeUnit'
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cxx_header = 'gpu-compute/compute_unit.hh'
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wavefronts = VectorParam.Wavefront('Number of wavefronts')
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# Wavefront size is 64. This is configurable, however changing
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# this value to anything other than 64 will likely cause errors.
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wf_size = Param.Int(64, 'Wavefront size (in work items)')
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num_SIMDs = Param.Int(4, 'number of SIMD units per CU')
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num_scalar_cores = Param.Int(1, 'number of Scalar cores per CU')
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num_scalar_mem_pipes = Param.Int(1, 'number of Scalar memory pipelines '\
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'per CU')
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simd_width = Param.Int(16, 'width (number of lanes) per SIMD unit')
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operand_network_length = Param.Int(1, 'number of pipe stages of operand '\
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'network')
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spbypass_pipe_length = Param.Int(4, 'vector ALU Single Precision bypass '\
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'latency')
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dpbypass_pipe_length = Param.Int(4, 'vector ALU Double Precision bypass '\
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'latency')
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scalar_pipe_length = Param.Int(1, 'number of pipe stages per scalar ALU')
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issue_period = Param.Int(4, 'number of cycles per issue period')
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vrf_gm_bus_latency = Param.Int(1, 'number of cycles per use of VRF to '\
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'GM bus')
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srf_scm_bus_latency = Param.Int(1, 'number of cycles per use of SRF '\
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'to Scalar Mem bus')
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vrf_lm_bus_latency = Param.Int(1, 'number of cycles per use of VRF to '\
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'LM bus')
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num_global_mem_pipes = Param.Int(1,'number of global memory pipes per CU')
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num_shared_mem_pipes = Param.Int(1,'number of shared memory pipes per CU')
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n_wf = Param.Int(10, 'Number of wavefront slots per SIMD')
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mem_req_latency = Param.Int(50, "Latency for request from the cu to ruby. "\
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"Represents the pipeline to reach the TCP "\
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"and specified in GPU clock cycles")
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mem_resp_latency = Param.Int(50, "Latency for responses from ruby to the "\
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"cu. Represents the pipeline between the "\
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"TCP and cu as well as TCP data array "\
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"access. Specified in GPU clock cycles")
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system = Param.System(Parent.any, "system object")
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cu_id = Param.Int('CU id')
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vrf_to_coalescer_bus_width = Param.Int(64, "VRF->Coalescer data bus "\
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"width in bytes")
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coalescer_to_vrf_bus_width = Param.Int(64, "Coalescer->VRF data bus "\
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"width in bytes")
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memory_port = VectorMasterPort("Port to the memory system")
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translation_port = VectorMasterPort('Port to the TLB hierarchy')
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sqc_port = MasterPort("Port to the SQC (I-cache")
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sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
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scalar_port = MasterPort("Port to the scalar data cache")
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scalar_tlb_port = MasterPort("Port to the TLB for the scalar data cache")
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perLaneTLB = Param.Bool(False, "enable per-lane TLB")
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prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\
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"(0 turns off prefetching)")
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prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)")
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prefetch_prev_type = Param.PrefetchType('PF_PHASE', "Prefetch the stride "\
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"from last mem req in lane of "\
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"CU|Phase|Wavefront")
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execPolicy = Param.String("OLDEST-FIRST", "WF execution selection policy");
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debugSegFault = Param.Bool(False, "enable debugging GPU seg faults")
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functionalTLB = Param.Bool(False, "Assume TLB causes no delay")
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localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\
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"kernel end")
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countPages = Param.Bool(False, "Generate per-CU file of all pages "\
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"touched and how many times")
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scalar_mem_queue_size = Param.Int(32, "Number of entries in scalar "\
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"memory pipeline's queues")
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global_mem_queue_size = Param.Int(256, "Number of entries in the global "
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"memory pipeline's queues")
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local_mem_queue_size = Param.Int(256, "Number of entries in the local "
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"memory pipeline's queues")
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max_wave_requests = Param.Int(64, "number of pending vector memory "\
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"requests per wavefront")
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max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the number"\
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" of instructions that can be sent to coalescer")
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ldsBus = Bridge() # the bridge between the CU and its LDS
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ldsPort = MasterPort("The port that goes to the LDS")
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localDataStore = Param.LdsState("the LDS for this CU")
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vector_register_file = VectorParam.VectorRegisterFile("Vector register "\
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"file")
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scalar_register_file = VectorParam.ScalarRegisterFile("Scalar register "\
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"file")
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out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery"
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" in the GM pipeline")
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register_manager = Param.RegisterManager("Register Manager")
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fetch_depth = Param.Int(2, 'number of i-cache lines that may be '
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'buffered in the fetch unit.')
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class Shader(ClockedObject):
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type = 'Shader'
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cxx_class = 'Shader'
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cxx_header = 'gpu-compute/shader.hh'
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CUs = VectorParam.ComputeUnit('Number of compute units')
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gpu_cmd_proc = Param.GPUCommandProcessor('Command processor for GPU')
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dispatcher = Param.GPUDispatcher('GPU workgroup dispatcher')
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n_wf = Param.Int(10, 'Number of wavefront slots per SIMD')
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impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into
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ruby at kernel boundaries""")
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globalmem = Param.MemorySize('64kB', 'Memory size')
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timing = Param.Bool(False, 'timing memory accesses')
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cpu_pointer = Param.BaseCPU(NULL, "pointer to base CPU")
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translation = Param.Bool(False, "address translation");
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timer_period = Param.Clock('10us', "system timer period")
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idlecu_timeout = Param.Tick(0, "Idle CU watchdog timeout threshold")
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max_valu_insts = Param.Int(0, "Maximum vALU insts before exiting")
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class GPUComputeDriver(HSADriver):
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type = 'GPUComputeDriver'
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cxx_header = 'gpu-compute/gpu_compute_driver.hh'
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class GPUDispatcher(SimObject):
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type = 'GPUDispatcher'
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cxx_header = 'gpu-compute/dispatcher.hh'
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class GPUCommandProcessor(HSADevice):
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type = 'GPUCommandProcessor'
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cxx_header = 'gpu-compute/gpu_command_processor.hh'
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dispatcher = Param.GPUDispatcher('workgroup dispatcher for the GPU')
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class StorageClassType(Enum): vals = [
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'SC_SPILL',
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'SC_GLOBAL',
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'SC_GROUP',
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'SC_PRIVATE',
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'SC_READONLY',
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'SC_KERNARG',
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'SC_ARG',
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'SC_NONE',
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]
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