Gabe Black 0cba96ba6a CPU: Merge the predecoder and decoder. ...

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc

2012-05-26 13:44:46 -07:00

..

base_dyn_inst.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

bpred_unit_impl.hh

BPred: Fix RAS to handle predicated call/return instructions.

2012-02-13 12:26:25 -06:00

bpred_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

bpred_unit.hh

BPred: Fix RAS to handle predicated call/return instructions.

2012-02-13 12:26:25 -06:00

checker_builder.cc

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

comm.hh

O3: When squashing, restore the macroop that should be used for fetching.

2011-08-14 17:41:34 -07:00

commit_impl.hh

O3/Ozone: Eliminate dead code counting software prefetch insts

2012-03-09 09:59:28 -05:00

commit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

commit.hh

cpu: add separate stats for insts/ops both globally and per cpu model

2012-02-12 16:07:39 -06:00

cpu_builder.cc

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

cpu_policy.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

cpu.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

cpu.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

decode_impl.hh

O3: Fix size of skid buffer between fetch and decode when widths are different

2012-03-21 10:34:05 -05:00

decode.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

decode.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

dep_graph.hh

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

2010-10-31 00:07:20 -07:00

dyn_inst_impl.hh

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

dyn_inst.cc

O3: Generaize the O3 IMPL class so it isn't split out by ISA.

2008-10-09 00:10:02 -07:00

dyn_inst.hh

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00

fetch_impl.hh

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

fetch.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

fetch.hh

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

free_list.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

free_list.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

fu_pool.cc

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

fu_pool.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

FuncUnitConfig.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

FUPool.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

iew_impl.hh

O3/Ozone: Eliminate dead code counting software prefetch insts

2012-03-09 09:59:28 -05:00

iew.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

iew.hh

Merge with head, hopefully the last time for this batch.

2012-01-31 22:40:08 -08:00

impl.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue_impl.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

inst_queue.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

isa_specific.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

lsq_impl.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

lsq_unit_impl.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

lsq_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq_unit.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

lsq.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

mem_dep_unit_impl.hh

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

mem_dep_unit.cc

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

mem_dep_unit.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

O3Checker.py

CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

2012-01-31 07:46:03 -08:00

O3CPU.py

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

regfile.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

rename_impl.hh

O3: Fix sizing of decode to rename skid buffer.

2012-03-21 10:34:06 -05:00

rename_map.cc

o3: missing newlines on some dprintfs

2011-06-10 22:15:32 -04:00

rename_map.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

rename.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rename.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

rob_impl.hh

O3 CPU: Provide the squashing instruction

2012-02-10 08:37:28 -06:00

rob.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rob.hh

O3 CPU: Provide the squashing instruction

2012-02-10 08:37:28 -06:00

sat_counter.cc

Merge ktlim@zizzer:/bk/newmem

2006-06-02 18:19:50 -04:00

sat_counter.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

SConscript

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

scoreboard.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

scoreboard.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

store_set.cc

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

store_set.hh

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

thread_context_impl.hh

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

thread_context.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

thread_context.hh

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

thread_state.hh

Implement Ali's review feedback.

2012-01-29 02:04:34 -08:00