b7b545bc38
This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
142 lines
4.5 KiB
C++
142 lines
4.5 KiB
C++
/*
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* Copyright (c) 2011 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_FETCH_UNIT_HH__
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#define __CPU_INORDER_FETCH_UNIT_HH__
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#include <list>
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#include <string>
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#include <vector>
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#include "arch/predecoder.hh"
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#include "arch/tlb.hh"
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#include "config/the_isa.hh"
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#include "cpu/decode.hh"
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#include "cpu/inorder/resources/cache_unit.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/port.hh"
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#include "params/InOrderCPU.hh"
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#include "sim/sim_object.hh"
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class FetchUnit : public CacheUnit
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{
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public:
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FetchUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
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virtual ~FetchUnit();
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typedef ThePipeline::DynInstPtr DynInstPtr;
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typedef TheISA::ExtMachInst ExtMachInst;
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struct FetchBlock {
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int asid;
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Addr addr;
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uint8_t *block;
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short cnt;
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bool valid;
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FetchBlock(int _asid, Addr _addr)
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: asid(_asid), addr(_addr), block(NULL), cnt(1), valid(false)
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{ }
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};
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/** Actions that this resource can take on an instruction */
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enum Command {
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InitiateFetch,
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CompleteFetch
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};
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ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num,
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unsigned cmd);
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/** Executes one of the commands from the "Command" enum */
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void execute(int slot_num);
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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Decoder decoder;
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private:
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void squashCacheRequest(CacheReqPtr req_ptr);
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void createMachInst(std::list<FetchBlock*>::iterator fetch_it,
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DynInstPtr inst);
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/** After memory request is completed, then turn the fetched data
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into an instruction.
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*/
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void processCacheCompletion(PacketPtr pkt);
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/** Create request that will interface w/TLB and Memory objects */
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virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
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int acc_size, int flags);
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/** Align a PC to the start of an I-cache block. */
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Addr cacheBlockAlignPC(Addr addr)
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{
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return (addr & ~(cacheBlkMask));
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}
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void removeAddrDependency(DynInstPtr inst);
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std::list<FetchBlock*>::iterator findReplacementBlock();
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std::list<FetchBlock*>::iterator findBlock(std::list<FetchBlock*>
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&fetch_blocks, int asid,
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Addr block_addr);
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void markBlockUsed(std::list<FetchBlock*>::iterator block_it);
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int blocksInUse();
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void clearFetchBuffer();
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int instSize;
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int fetchBuffSize;
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TheISA::Predecoder *predecoder[ThePipeline::MaxThreads];
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/** Valid Cache Blocks*/
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std::list<FetchBlock*> fetchBuffer;
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/** Cache lines that are pending */
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std::list<FetchBlock*> pendingFetch;
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};
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#endif //__CPU_FETCH_UNIT_HH__
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