91d83cc8a1
The create() method on Params structs usually instantiate SimObjects using a constructor which takes the Params struct as a parameter somehow. There has been a lot of needless variation in how that was done, making it annoying to pass Params down to base classes. Some of the different forms were: const Params & Params & Params * const Params * Params const* This change goes through and fixes up every constructor and every create() method to use the const Params & form. We use a reference because the Params struct should never be null. We use const because neither the create method nor the consuming object should modify the record of the parameters as they came in from the config. That would make consuming them not idempotent, and make it impossible to tell what the actual simulation configuration was since it would change from any user visible form (config script, config.ini, dot pdf output). Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
229 lines
8.4 KiB
C++
229 lines
8.4 KiB
C++
/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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*
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* Fetch2 receives lines of data from Fetch1, separates them into
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* instructions and passes them to Decode
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*/
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#ifndef __CPU_MINOR_FETCH2_HH__
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#define __CPU_MINOR_FETCH2_HH__
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#include "cpu/minor/buffers.hh"
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#include "cpu/minor/cpu.hh"
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#include "cpu/minor/pipe_data.hh"
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#include "cpu/pred/bpred_unit.hh"
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#include "params/MinorCPU.hh"
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namespace Minor
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{
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/** This stage receives lines of data from Fetch1, separates them into
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* instructions and passes them to Decode */
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class Fetch2 : public Named
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{
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protected:
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/** Pointer back to the containing CPU */
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MinorCPU &cpu;
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/** Input port carrying lines from Fetch1 */
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Latch<ForwardLineData>::Output inp;
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/** Input port carrying branches from Execute. This is a snoop of the
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* data provided to F1. */
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Latch<BranchData>::Output branchInp;
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/** Output port carrying predictions back to Fetch1 */
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Latch<BranchData>::Input predictionOut;
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/** Output port carrying instructions into Decode */
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Latch<ForwardInstData>::Input out;
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/** Interface to reserve space in the next stage */
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std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;
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/** Width of output of this stage/input of next in instructions */
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unsigned int outputWidth;
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/** If true, more than one input word can be processed each cycle if
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* there is room in the output to contain its processed data */
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bool processMoreThanOneInput;
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/** Branch predictor passed from Python configuration */
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BPredUnit &branchPredictor;
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public:
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/* Public so that Pipeline can pass it to Fetch1 */
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std::vector<InputBuffer<ForwardLineData>> inputBuffer;
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protected:
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/** Data members after this line are cycle-to-cycle state */
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struct Fetch2ThreadInfo {
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/** Default constructor */
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Fetch2ThreadInfo() :
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inputIndex(0),
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pc(TheISA::PCState(0)),
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havePC(false),
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lastStreamSeqNum(InstId::firstStreamSeqNum),
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fetchSeqNum(InstId::firstFetchSeqNum),
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expectedStreamSeqNum(InstId::firstStreamSeqNum),
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predictionSeqNum(InstId::firstPredictionSeqNum),
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blocked(false)
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{ }
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Fetch2ThreadInfo(const Fetch2ThreadInfo& other) :
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inputIndex(other.inputIndex),
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pc(other.pc),
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havePC(other.havePC),
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lastStreamSeqNum(other.lastStreamSeqNum),
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expectedStreamSeqNum(other.expectedStreamSeqNum),
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predictionSeqNum(other.predictionSeqNum),
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blocked(other.blocked)
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{ }
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/** Index into an incompletely processed input line that instructions
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* are to be extracted from */
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unsigned int inputIndex;
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/** Remembered program counter value. Between contiguous lines, this
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* is just updated with advancePC. For lines following changes of
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* stream, a new PC must be loaded and havePC be set.
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* havePC is needed to accomodate instructions which span across
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* lines meaning that Fetch2 and the decoder need to remember a PC
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* value and a partially-offered instruction from the previous line */
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TheISA::PCState pc;
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/** PC is currently valid. Initially false, gets set to true when a
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* change-of-stream line is received and false again when lines are
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* discarded for any reason */
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bool havePC;
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/** Stream sequence number of the last seen line used to identify
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* changes of instruction stream */
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InstSeqNum lastStreamSeqNum;
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/** Fetch2 is the source of fetch sequence numbers. These represent the
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* sequence that instructions were extracted from fetched lines. */
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InstSeqNum fetchSeqNum;
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/** Stream sequence number remembered from last time the
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* predictionSeqNum changed. Lines should only be discarded when their
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* predictionSeqNums disagree with Fetch2::predictionSeqNum *and* they
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* are from the same stream that bore that prediction number */
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InstSeqNum expectedStreamSeqNum;
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/** Fetch2 is the source of prediction sequence numbers. These
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* represent predicted changes of control flow sources from branch
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* prediction in Fetch2. */
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InstSeqNum predictionSeqNum;
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/** Blocked indication for report */
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bool blocked;
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};
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std::vector<Fetch2ThreadInfo> fetchInfo;
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ThreadID threadPriority;
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struct Fetch2Stats : public Stats::Group
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{
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Fetch2Stats(MinorCPU *cpu);
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/** Stats */
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Stats::Scalar intInstructions;
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Stats::Scalar fpInstructions;
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Stats::Scalar vecInstructions;
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Stats::Scalar loadInstructions;
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Stats::Scalar storeInstructions;
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Stats::Scalar amoInstructions;
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} stats;
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protected:
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/** Get a piece of data to work on from the inputBuffer, or 0 if there
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* is no data. */
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const ForwardLineData *getInput(ThreadID tid);
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/** Pop an element off the input buffer, if there are any */
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void popInput(ThreadID tid);
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/** Dump the whole contents of the input buffer. Useful after a
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* prediction changes control flow */
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void dumpAllInput(ThreadID tid);
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/** Update local branch prediction structures from feedback from
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* Execute. */
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void updateBranchPrediction(const BranchData &branch);
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/** Predicts branches for the given instruction. Updates the
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* instruction's predicted... fields and also the branch which
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* carries the prediction to Fetch1 */
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void predictBranch(MinorDynInstPtr inst, BranchData &branch);
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/** Use the current threading policy to determine the next thread to
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* fetch from. */
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ThreadID getScheduledThread();
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public:
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Fetch2(const std::string &name,
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MinorCPU &cpu_,
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const MinorCPUParams ¶ms,
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Latch<ForwardLineData>::Output inp_,
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Latch<BranchData>::Output branchInp_,
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Latch<BranchData>::Input predictionOut_,
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Latch<ForwardInstData>::Input out_,
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std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
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public:
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/** Pass on input/buffer data to the output if you can */
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void evaluate();
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void minorTrace() const;
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/** Is this stage drained? For Fetch2, draining is initiated by
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* Execute halting Fetch1 causing Fetch2 to naturally drain.
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* Branch predictions are ignored by Fetch1 during halt */
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bool isDrained();
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};
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}
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#endif /* __CPU_MINOR_FETCH2_HH__ */
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