d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
142 lines
4.5 KiB
Python
142 lines
4.5 KiB
Python
import argparse
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import subprocess
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import sys
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from pprint import pprint
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import m5
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from m5.objects import *
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from m5.util import *
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addToPath("../")
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from common import (
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HMC,
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MemConfig,
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)
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def add_options(parser):
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parser.add_argument(
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"--external-memory-system",
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default=0,
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action="store",
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type=int,
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help="External memory system",
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)
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# TLM related options, currently optional in configs/common/MemConfig.py
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parser.add_argument(
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"--tlm-memory",
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action="store_true",
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help="use\
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external port for SystemC TLM co-simulation. Default:\
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no",
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)
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# Elastic traces related options, currently optional in
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# configs/common/MemConfig.py
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parser.add_argument(
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"--elastic-trace-en",
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action="store_true",
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help="enable capture of data dependency and\
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instruction fetch traces using elastic trace\
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probe.\nDefault: no",
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)
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# Options related to traffic generation
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parser.add_argument(
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"--num-tgen",
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default=4,
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action="store",
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type=int,
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choices=[4],
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help="number of traffic generators.\
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Right now this script supports only 4.\nDefault: 4",
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)
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parser.add_argument(
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"--tgen-cfg-file",
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default="./configs/example/hmc_tgen.cfg",
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type=str,
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help="Traffic generator(s) configuration\
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file. Note: this script uses the same configuration\
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file for all traffic generators",
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)
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# considering 4GB HMC device with following parameters
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# hmc_device_size = '4GB'
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# hmc_vault_size = '256MB'
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# hmc_stack_size = 8
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# hmc_bank_in_stack = 2
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# hmc_bank_size = '16MB'
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# hmc_bank_in_vault = 16
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def build_system(options):
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# create the system we are going to simulate
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system = System()
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# use timing mode for the interaction between requestor-responder ports
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system.mem_mode = "timing"
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# set the clock frequency of the system
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clk = "100GHz"
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vd = VoltageDomain(voltage="1V")
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system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
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# add traffic generators to the system
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system.tgen = [
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TrafficGen(config_file=options.tgen_cfg_file)
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for i in range(options.num_tgen)
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]
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# Config memory system with given HMC arch
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MemConfig.config_mem(options, system)
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# Connect the traffic generatiors
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if options.arch == "distributed":
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for i in range(options.num_tgen):
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system.tgen[i].port = system.membus.cpu_side_ports
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.cpu_side_ports
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if options.arch == "mixed":
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for i in range(int(options.num_tgen / 2)):
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system.tgen[i].port = system.membus.cpu_side_ports
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hh = system.hmc_host
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if options.enable_global_monitor:
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system.tgen[2].port = hh.lmonitor[2].cpu_side_port
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hh.lmonitor[2].mem_side_port = hh.seriallink[2].cpu_side_port
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system.tgen[3].port = hh.lmonitor[3].cpu_side_port
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hh.lmonitor[3].mem_side_port = hh.seriallink[3].cpu_side_port
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else:
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system.tgen[2].port = hh.seriallink[2].cpu_side_port
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system.tgen[3].port = hh.seriallink[3].cpu_side_port
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.cpu_side_ports
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if options.arch == "same":
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hh = system.hmc_host
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for i in range(options.num_links_controllers):
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if options.enable_global_monitor:
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system.tgen[i].port = hh.lmonitor[i].cpu_side_port
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else:
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system.tgen[i].port = hh.seriallink[i].cpu_side_port
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# set up the root SimObject
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root = Root(full_system=False, system=system)
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return root
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def main():
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parser = argparse.ArgumentParser(
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description="Simple system using HMC as\
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main memory"
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)
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HMC.add_options(parser)
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add_options(parser)
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options = parser.parse_args()
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# build the system
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root = build_system(options)
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# instantiate all of the objects we've created so far
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m5.instantiate()
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print("Beginning simulation!")
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event = m5.simulate(10000000000)
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m5.stats.dump()
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print(
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"Exiting @ tick %i because %s (exit code is %i)"
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% (m5.curTick(), event.getCause(), event.getCode())
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)
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print("Done")
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if __name__ == "__m5_main__":
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main()
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