7137b73ca0
Introduced in #1234, this caused compilation to faill in Apple Silicon systems. This bug is the same as #582 where a more detailed explanation is provided.
545 lines
16 KiB
C++
545 lines
16 KiB
C++
/*
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* Copyright (c) 2016-2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU__REG_CLASS_HH__
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#define __CPU__REG_CLASS_HH__
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#include <cstddef>
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#include <iterator>
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#include <string>
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#include "arch/generic/vec_reg.hh"
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#include "base/cprintf.hh"
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#include "base/debug.hh"
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#include "base/intmath.hh"
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#include "base/types.hh"
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#include "debug/InvalidReg.hh"
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namespace gem5
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{
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/** Enumerate the classes of registers. */
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enum RegClassType
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{
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IntRegClass, ///< Integer register
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FloatRegClass, ///< Floating-point register
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/** Vector Register. */
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VecRegClass,
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/** Vector Register Native Elem lane. */
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VecElemClass,
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VecPredRegClass,
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MatRegClass, ///< Matrix Register
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CCRegClass, ///< Condition-code register
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MiscRegClass, ///< Control (misc) register
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InvalidRegClass = -1
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};
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// "Standard" register class names. Using these is encouraged but optional.
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inline constexpr char IntRegClassName[] = "integer";
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inline constexpr char FloatRegClassName[] = "floating_point";
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inline constexpr char VecRegClassName[] = "vector";
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inline constexpr char VecElemClassName[] = "vector_element";
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inline constexpr char VecPredRegClassName[] = "vector_predicate";
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inline constexpr char MatRegClassName[] = "matrix";
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inline constexpr char CCRegClassName[] = "condition_code";
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inline constexpr char MiscRegClassName[] = "miscellaneous";
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class RegClass;
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class RegClassIterator;
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class BaseISA;
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/** Register ID: describe an architectural register with its class and index.
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* This structure is used instead of just the register index to disambiguate
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* between different classes of registers. For example, a integer register with
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* index 3 is represented by Regid(IntRegClass, 3).
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*/
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class RegId
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{
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protected:
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const RegClass *_regClass = nullptr;
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RegIndex regIdx;
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int numPinnedWrites;
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friend struct std::hash<RegId>;
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friend class RegClassIterator;
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public:
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inline constexpr RegId();
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constexpr RegId(const RegClass ®_class, RegIndex reg_idx)
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: _regClass(®_class), regIdx(reg_idx), numPinnedWrites(0)
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{}
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constexpr operator RegIndex() const
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{
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return index();
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}
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constexpr bool
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operator==(const RegId& that) const
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{
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return classValue() == that.classValue() && regIdx == that.index();
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}
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constexpr bool
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operator!=(const RegId& that) const
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{
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return !(*this==that);
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}
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/** Order operator.
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* The order is required to implement maps with key type RegId
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*/
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constexpr bool
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operator<(const RegId& that) const
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{
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return classValue() < that.classValue() ||
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(classValue() == that.classValue() && (regIdx < that.index()));
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}
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/**
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* Return true if this register can be renamed
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*/
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constexpr bool
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isRenameable() const
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{
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return classValue() != MiscRegClass && classValue() != InvalidRegClass;
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}
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/** @return true if it is of the specified class. */
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inline constexpr bool is(RegClassType reg_class) const;
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/** Index accessors */
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/** @{ */
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constexpr RegIndex index() const { return regIdx; }
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/** Class accessor */
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constexpr const RegClass ®Class() const { return *_regClass; }
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inline constexpr RegClassType classValue() const;
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/** Return a const char* with the register class name. */
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inline constexpr const char* className() const;
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inline constexpr bool isFlat() const;
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inline RegId flatten(const BaseISA &isa) const;
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int getNumPinnedWrites() const { return numPinnedWrites; }
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void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
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friend inline std::ostream& operator<<(std::ostream& os, const RegId& rid);
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};
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class RegClassOps
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{
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public:
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/** Print the name of the register specified in id. */
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virtual std::string regName(const RegId &id) const;
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/** Print the value of a register pointed to by val of size size. */
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virtual std::string valString(const void *val, const size_t& size) const;
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/** Flatten register id id using information in the ISA object isa. */
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virtual RegId
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flatten(const BaseISA &isa, const RegId &id) const
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{
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return id;
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}
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};
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class RegClassIterator;
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class RegClass
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{
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private:
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RegClassType _type;
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const char *_name;
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size_t _numRegs;
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size_t _regBytes = sizeof(RegVal);
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// This is how much to shift an index by to get an offset of a register in
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// a register file from the register index, which would otherwise need to
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// be calculated with a multiply.
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size_t _regShift = ceilLog2(sizeof(RegVal));
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static inline RegClassOps defaultOps;
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const RegClassOps *_ops = &defaultOps;
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const debug::Flag &debugFlag;
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bool _flat = true;
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public:
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constexpr RegClass(RegClassType type, const char *new_name,
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size_t num_regs, const debug::Flag &debug_flag) :
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_type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag)
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{}
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constexpr RegClass
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needsFlattening() const
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{
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RegClass reg_class = *this;
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reg_class._flat = false;
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return reg_class;
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}
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constexpr RegClass
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ops(const RegClassOps &new_ops) const
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{
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RegClass reg_class = *this;
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reg_class._ops = &new_ops;
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return reg_class;
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}
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template <class RegType>
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constexpr RegClass
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regType() const
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{
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RegClass reg_class = *this;
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reg_class._regBytes = sizeof(RegType);
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reg_class._regShift = ceilLog2(reg_class._regBytes);
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return reg_class;
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}
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constexpr RegClassType type() const { return _type; }
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constexpr const char *name() const { return _name; }
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constexpr size_t numRegs() const { return _numRegs; }
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constexpr size_t regBytes() const { return _regBytes; }
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constexpr size_t regShift() const { return _regShift; }
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constexpr const debug::Flag &debug() const { return debugFlag; }
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constexpr bool isFlat() const { return _flat; }
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std::string regName(const RegId &id) const { return _ops->regName(id); }
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std::string
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valString(const void *val) const
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{
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return _ops->valString(val, regBytes());
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}
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std::string
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valString(const void *val, const size_t& num_bytes) const
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{
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return _ops->valString(val, std::min(regBytes(), num_bytes));
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}
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RegId
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flatten(const BaseISA &isa, const RegId &id) const
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{
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return isFlat() ? id : _ops->flatten(isa, id);
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}
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using iterator = RegClassIterator;
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inline iterator begin() const;
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inline iterator end() const;
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inline constexpr RegId operator[](RegIndex idx) const;
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};
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inline constexpr RegClass
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invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
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constexpr RegId::RegId() : RegId(invalidRegClass, 0) {}
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constexpr bool
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RegId::is(RegClassType reg_class) const
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{
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return _regClass->type() == reg_class;
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}
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constexpr RegClassType RegId::classValue() const { return _regClass->type(); }
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constexpr const char* RegId::className() const { return _regClass->name(); }
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constexpr bool RegId::isFlat() const { return _regClass->isFlat(); }
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RegId
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RegId::flatten(const BaseISA &isa) const
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{
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return _regClass->flatten(isa, *this);
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}
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std::ostream&
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operator<<(std::ostream& os, const RegId& rid)
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{
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return os << rid.regClass().regName(rid);
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}
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class RegClassIterator
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{
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private:
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RegId id;
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RegClassIterator(const RegClass ®_class, RegIndex idx) :
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id(reg_class, idx)
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{}
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friend class RegClass;
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public:
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using iterator_category = std::forward_iterator_tag;
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using difference_type = std::size_t;
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using value_type = const RegId;
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using pointer = value_type *;
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using reference = value_type &;
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reference operator*() const { return id; }
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pointer operator->() { return &id; }
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RegClassIterator &
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operator++()
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{
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id.regIdx++;
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return *this;
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}
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RegClassIterator
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operator++(int)
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{
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auto tmp = *this;
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++(*this);
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return tmp;
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}
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bool
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operator==(const RegClassIterator &other) const
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{
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return id == other.id;
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}
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bool
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operator!=(const RegClassIterator &other) const
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{
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return id != other.id;
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}
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};
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RegClassIterator
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RegClass::begin() const
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{
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return RegClassIterator(*this, 0);
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}
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RegClassIterator
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RegClass::end() const
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{
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return RegClassIterator(*this, numRegs());
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}
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constexpr RegId
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RegClass::operator[](RegIndex idx) const
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{
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return RegId(*this, idx);
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}
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// Type matching for gem5::VecRegContainer class
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// This is used in TypedRegClassOps.
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template<typename>
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struct is_vec_reg_container : std::false_type {};
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template<std::size_t SIZE>
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struct is_vec_reg_container<gem5::VecRegContainer<SIZE>> : std::true_type {};
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template <typename ValueType>
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class TypedRegClassOps : public RegClassOps
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{
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public:
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std::string
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valString(const void *val, const size_t& size) const override
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{
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if constexpr (is_vec_reg_container<ValueType>::value) {
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if (size == sizeof(ValueType)) {
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return csprintf("%s", *(const ValueType *)val);
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} else {
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return ((const ValueType *)val)->getString(size);
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}
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} else {
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assert(size == sizeof(ValueType));
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return csprintf("%s", *(const ValueType *)val);
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}
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}
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};
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template <typename ValueType>
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class VecElemRegClassOps : public TypedRegClassOps<ValueType>
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{
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protected:
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size_t elemsPerVec;
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public:
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explicit VecElemRegClassOps(size_t elems_per_vec) :
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elemsPerVec(elems_per_vec)
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{}
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std::string
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regName(const RegId &id) const override
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{
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RegIndex reg_idx = id.index() / elemsPerVec;
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RegIndex elem_idx = id.index() % elemsPerVec;
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return csprintf("v%d[%d]", reg_idx, elem_idx);
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}
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};
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/** Physical register ID.
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* Like a register ID but physical. The inheritance is private because the
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* only relationship between this types is functional, and it is done to
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* prevent code replication. */
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class PhysRegId : private RegId
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{
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private:
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RegIndex flatIdx;
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int numPinnedWritesToComplete;
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bool pinned;
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public:
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explicit PhysRegId() : RegId(invalidRegClass, -1), flatIdx(-1),
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numPinnedWritesToComplete(0)
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{}
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/** Scalar PhysRegId constructor. */
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explicit PhysRegId(const RegClass ®_class, RegIndex _regIdx,
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RegIndex _flatIdx)
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: RegId(reg_class, _regIdx), flatIdx(_flatIdx),
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numPinnedWritesToComplete(0), pinned(false)
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{}
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/** Visible RegId methods */
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/** @{ */
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using RegId::index;
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using RegId::regClass;
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using RegId::classValue;
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using RegId::className;
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using RegId::is;
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/** @} */
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/**
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* Explicit forward methods, to prevent comparisons of PhysRegId with
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* RegIds.
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*/
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/** @{ */
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bool
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operator<(const PhysRegId& that) const
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{
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return RegId::operator<(that);
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}
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bool
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operator==(const PhysRegId& that) const
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{
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return RegId::operator==(that);
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}
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bool
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operator!=(const PhysRegId& that) const
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{
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return RegId::operator!=(that);
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}
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/** @} */
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/**
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* Returns true if this register is always associated to the same
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* architectural register.
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*/
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bool isFixedMapping() const { return !isRenameable(); }
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/** Flat index accessor */
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const RegIndex& flatIndex() const { return flatIdx; }
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int getNumPinnedWrites() const { return numPinnedWrites; }
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void
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setNumPinnedWrites(int numWrites)
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{
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// An instruction with a pinned destination reg can get
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// squashed. The numPinnedWrites counter may be zero when
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// the squash happens but we need to know if the dest reg
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// was pinned originally in order to reset counters properly
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// for a possible re-rename using the same physical reg (which
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// may be required in case of a mem access order violation).
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pinned = (numWrites != 0);
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numPinnedWrites = numWrites;
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}
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void decrNumPinnedWrites() { --numPinnedWrites; }
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void incrNumPinnedWrites() { ++numPinnedWrites; }
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bool isPinned() const { return pinned; }
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int
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getNumPinnedWritesToComplete() const
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{
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return numPinnedWritesToComplete;
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}
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void
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setNumPinnedWritesToComplete(int numWrites)
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{
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numPinnedWritesToComplete = numWrites;
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}
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void decrNumPinnedWritesToComplete() { --numPinnedWritesToComplete; }
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void incrNumPinnedWritesToComplete() { ++numPinnedWritesToComplete; }
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};
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using PhysRegIdPtr = PhysRegId*;
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} // namespace gem5
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namespace std
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{
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template<>
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struct hash<gem5::RegId>
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{
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size_t
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operator()(const gem5::RegId& reg_id) const
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{
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// Extract unique integral values for the effective fields of a RegId.
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const size_t index = static_cast<size_t>(reg_id.index());
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const size_t class_num = static_cast<size_t>(reg_id.classValue());
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const size_t shifted_class_num =
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class_num << (sizeof(gem5::RegIndex) << 3);
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// Concatenate the class_num to the end of the flat_index, in order to
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// maximize information retained.
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const size_t concatenated_hash = index | shifted_class_num;
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// If RegIndex is larger than size_t, then class_num will not be
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// considered by this hash function, so we may wish to perform a
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// different operation to include that information in the hash.
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static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
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"sizeof(RegIndex) should be less than sizeof(size_t)");
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return concatenated_hash;
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}
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};
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} // namespace std
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#endif // __CPU__REG_CLASS_HH__
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