07ea0891f1
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
140 lines
5.0 KiB
Ruby
140 lines
5.0 KiB
Ruby
#!/usr/bin/ruby
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#
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# Creates a homogeneous CMP system with a single unified cache per
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# core and a crossbar network. Uses the default parameters listed
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# below, which can be overridden using command line args.
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#
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require "cfg.rb"
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RubySystem.reset
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# default values
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num_cores = 2
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l1_icache_size_kb = 64
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l1_icache_assoc = 8
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l1_icache_latency = 1
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l1_dcache_size_kb = 32
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l1_dcache_assoc = 8
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l1_dcache_latency = 1
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l2_cache_size_kb = 8192 # total size (sum of all banks)
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l2_cache_assoc = 16
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l2_cache_latency = 12
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num_l2_banks = num_cores
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num_memories = 1
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memory_size_mb = 1024
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num_dma = 1
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#default protocol
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protocol = "MOESI_CMP_directory"
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# check for overrides
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for i in 0..$*.size-1 do
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if $*[i] == "-c" or $*[i] == "--protocol"
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i += 1
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protocol = $*[i]
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elsif $*[i] == "-A"
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l1_dcache_size_kb = $*[i+1].to_i
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i = i+1
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elsif $*[i] == "-B"
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num_l2_banks = $*[i+1].to_i
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i = i+1
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elsif $*[i] == "-m"
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num_memories = $*[i+1].to_i
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i = i+1
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elsif $*[i] == "-p"
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num_cores = $*[i+1].to_i
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i = i+1
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elsif $*[i] == "-R"
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if $*[i+1] == "rand"
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RubySystem.random_seed = "rand"
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else
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RubySystem.random_seed = $*[i+1].to_i
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end
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i = i+ 1
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elsif $*[i] == "-s"
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memory_size_mb = $*[i+1].to_i
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i = i + 1
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end
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end
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net_ports = Array.new
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iface_ports = Array.new
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assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol '#{protocol}'");
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require protocol+".rb"
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num_cores.times { |n|
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icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb*1024, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU")
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dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb*1024, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU")
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sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache)
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iface_ports << sequencer
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if protocol == "MOESI_CMP_directory"
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net_ports << MOESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
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"L1Cache",
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icache, dcache,
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sequencer,
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num_l2_banks)
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
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"L1Cache",
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icache, dcache,
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sequencer,
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num_l2_banks)
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end
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}
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num_l2_banks.times { |n|
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cache = SetAssociativeCache.new("l2u_"+n.to_s, (l2_cache_size_kb*1024)/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU")
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if protocol == "MOESI_CMP_directory"
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net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
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"L2Cache",
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cache)
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
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"L2Cache",
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cache)
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end
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net_ports.last.request_latency = l2_cache_latency + 2
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net_ports.last.response_latency = l2_cache_latency + 2
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}
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num_memories.times { |n|
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directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
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memory_control = MemoryControl.new("MemoryControl_"+n.to_s)
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if protocol == "MOESI_CMP_directory"
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net_ports << MOESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
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"Directory",
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directory,
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memory_control)
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
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"Directory",
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directory,
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memory_control)
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end
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}
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num_dma.times { |n|
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dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
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iface_ports << dma_sequencer
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if protocol == "MOESI_CMP_directory"
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net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
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"DMA",
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dma_sequencer)
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
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"DMA",
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dma_sequencer)
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end
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}
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topology = CrossbarTopology.new("theTopology", net_ports)
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on_chip_net = Network.new("theNetwork", topology)
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RubySystem.init(iface_ports, on_chip_net)
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