Ruslan Bukin b3314673f4 dev: Extend access width for IDE control registers ...

Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl
register as FreeBSD required.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

2015-04-03 11:42:10 -05:00

..

arch

x86: fix debug trace output for mwait

2015-04-03 11:42:10 -05:00

base

base: Add compiler macros to add deprecation warnings

2015-02-11 10:23:24 -05:00

cpu

cpu: fix system total instructions accounting

2015-04-03 11:42:10 -05:00

dev

dev: Extend access width for IDE control registers

2015-04-03 11:42:10 -05:00

doc

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

misc: Move AddrRangeList from port.hh to addr_range.hh

2014-10-16 05:49:59 -04:00

mem

mem: Support any number of master-IDs in stride prefetcher

2015-03-27 04:56:03 -04:00

proto

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

python

misc: quote args in echoed command line

2015-03-23 16:14:18 -07:00

sim

sim: Update limit_event reuse to final version

2015-03-26 11:16:44 -04:00

unittest

test: Add a unittest for the BitUnion types.

2015-01-07 00:34:40 -08:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

base: Add compiler macros to add deprecation warnings

2015-02-11 10:23:24 -05:00