This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
221 lines
7.7 KiB
Python
221 lines
7.7 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import sys
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import os
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import re
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Import('*')
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#################################################################
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#
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# ISA "switch header" generation.
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#
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# Auto-generate arch headers that include the right ISA-specific
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# header based on the setting of THE_ISA preprocessor variable.
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#
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#################################################################
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env.SwitchingHeaders(
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Split('''
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decoder.hh
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interrupts.hh
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isa.hh
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isa_traits.hh
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kernel_stats.hh
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locked_mem.hh
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microcode_rom.hh
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mmapped_ipr.hh
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mt.hh
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process.hh
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pseudo_inst.hh
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registers.hh
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remote_gdb.hh
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stacktrace.hh
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tlb.hh
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types.hh
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utility.hh
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vtophys.hh
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'''),
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env.subst('${TARGET_ISA}'))
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if env['BUILD_GPU']:
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env.SwitchingHeaders(
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Split('''
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gpu_decoder.hh
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gpu_isa.hh
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gpu_types.hh
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'''),
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env.subst('${TARGET_GPU_ISA}'))
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#################################################################
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#
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# Include architecture-specific files.
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#
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#################################################################
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#
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# Build a SCons scanner for ISA files
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#
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import SCons.Scanner
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isa_scanner = SCons.Scanner.Classic("ISAScan",
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[".isa", ".ISA"],
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"SRCDIR",
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r'^\s*##include\s+"([\w/.-]*)"')
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env.Append(SCANNERS = isa_scanner)
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#
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# Now create a Builder object that uses isa_parser.py to generate C++
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# output from the ISA description (*.isa) files.
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#
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isa_parser = File('isa_parser.py')
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# The emitter patches up the sources & targets to include the
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# autogenerated files as targets and isa parser itself as a source.
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def isa_desc_emitter(target, source, env):
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# List the isa parser as a source.
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source += [
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isa_parser,
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Value("ExecContext"),
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]
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# Specify different targets depending on if we're running the ISA
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# parser for its dependency information, or for the generated files.
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# (As an optimization, the ISA parser detects the useless second run
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# and skips doing any work, if the first run was performed, since it
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# always generates all its files). The way we track this in SCons is the
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# <arch>_isa_outputs value in the environment (env). If it's unset, we
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# don't know what the dependencies are so we ask for generated/inc.d to
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# be generated so they can be acquired. If we know what they are, then
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# it's because we've already processed inc.d and then claim that our
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# outputs (targets) will be thus.
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isa = env['TARGET_ISA']
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key = '%s_isa_outputs' % isa
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if key in env:
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targets = [ os.path.join('generated', f) for f in env[key] ]
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else:
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targets = [ os.path.join('generated','inc.d') ]
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def prefix(s):
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return os.path.join(target[0].dir.up().abspath, s)
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return [ prefix(t) for t in targets ], source
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ARCH_DIR = Dir('.')
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# import ply here because SCons screws with sys.path when performing actions.
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import ply
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def isa_desc_action_func(target, source, env):
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# Add the current directory to the system path so we can import files
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sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
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import isa_parser
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# Skip over the ISA description itself and the parser to the CPU models.
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models = [ s.get_contents() for s in source[2:] ]
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parser = isa_parser.ISAParser(target[0].dir.abspath)
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parser.parse_isa_desc(source[0].abspath)
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isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
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# Also include the CheckerCPU as one of the models if it is being
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# enabled via command line.
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isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
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env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
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# The ISA is generated twice: the first time to find out what it generates,
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# and the second time to make scons happy by telling the ISADesc builder
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# what it will make before it builds it.
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def scan_isa_deps(target, source, env):
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# Process dependency file generated by the ISA parser --
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# add the listed files to the dependency tree of the build.
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source = source[0]
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archbase = source.dir.up().path
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try:
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depfile = open(source.abspath, 'r')
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except:
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print "scan_isa_deps: Can't open ISA deps file '%s' in %s" % \
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(source.path,os.getcwd())
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raise
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# Scan through the lines
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targets = {}
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for line in depfile:
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# Read the dependency line with the format
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# <target file>: [ <dependent file>* ]
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m = re.match(r'^\s*([^:]+\.([^\.:]+))\s*:\s*(.*)', line)
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assert(m)
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targ, extn = m.group(1,2)
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deps = m.group(3).split()
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files = [ targ ] + deps
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for f in files:
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targets[f] = True
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# Eliminate unnecessary re-generation if we already generated it
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env.Precious(os.path.join(archbase, 'generated', f))
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files = [ os.path.join(archbase, 'generated', f) for f in files ]
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if extn == 'cc':
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Source(os.path.join(archbase,'generated', targ))
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depfile.close()
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env[env['TARGET_ISA'] + '_isa_outputs'] = targets.keys()
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isa = env.ISADesc(os.path.join(archbase,'isa','main.isa'))
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for t in targets:
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env.Depends('#all-isas', isa)
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env.Append(BUILDERS = {'ScanISA' :
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Builder(action=MakeAction(scan_isa_deps,
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Transform("NEW DEPS", 1)))})
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DebugFlag('IntRegs')
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DebugFlag('FloatRegs')
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DebugFlag('VecRegs')
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DebugFlag('CCRegs')
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DebugFlag('MiscRegs')
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CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
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