Derek Christ
bc6133e6a1
Add a DRAMSys wrapper to the gem5 memory source that instantiates the DRAMSys simulator. Another DRAMSys SimObject implements the AbstractMemory interface and exposes the tlm target socket. Change-Id: I8a95e729905e0924453043e5e7744df7a7ce4548 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62912 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
/*
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* Copyright (c) 2022 Fraunhofer IESE
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dramsys_wrapper.hh"
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namespace gem5
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{
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namespace memory
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{
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DRAMSysWrapper::DRAMSysWrapper(
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sc_core::sc_module_name name,
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DRAMSysConfiguration::Configuration const &config,
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bool recordable,
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AddrRange range) :
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sc_core::sc_module(name),
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dramsys(instantiateDRAMSys(recordable, config)),
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range(range)
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{
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tSocket.register_nb_transport_fw(this, &DRAMSysWrapper::nb_transport_fw);
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tSocket.register_transport_dbg(this, &DRAMSysWrapper::transport_dbg);
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iSocket.register_nb_transport_bw(this, &DRAMSysWrapper::nb_transport_bw);
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iSocket.bind(dramsys->tSocket);
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// Register a callback to compensate for the destructor not
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// being called.
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registerExitCallback(
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[this]()
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{
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// Workaround for BUG GEM5-1233
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sc_gem5::Kernel::stop();
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});
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}
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std::shared_ptr<::DRAMSys>
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DRAMSysWrapper::instantiateDRAMSys(
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bool recordable,
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DRAMSysConfiguration::Configuration const &config)
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{
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return recordable
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? std::make_shared<::DRAMSysRecordable>("DRAMSys", config)
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: std::make_shared<::DRAMSys>("DRAMSys", config);
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}
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tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_fw(
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tlm::tlm_generic_payload &payload,
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tlm::tlm_phase &phase,
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sc_core::sc_time &fwDelay)
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{
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// Subtract base address offset
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payload.set_address(payload.get_address() - range.start());
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return iSocket->nb_transport_fw(payload, phase, fwDelay);
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}
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tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_bw(
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tlm::tlm_generic_payload &payload,
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tlm::tlm_phase &phase,
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sc_core::sc_time &bwDelay)
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{
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return tSocket->nb_transport_bw(payload, phase, bwDelay);
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}
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unsigned int DRAMSysWrapper::transport_dbg(tlm::tlm_generic_payload &trans)
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{
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// Subtract base address offset
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trans.set_address(trans.get_address() - range.start());
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return iSocket->transport_dbg(trans);
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}
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} // namespace memory
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} // namespace gem5
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