a7ef5b77d6
Change-Id: I5ff62b03c34e41395a957a0799925ddd9c275458 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67291 Reviewed-by: Nicolas Boichat <drinkcat@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@google.com>
346 lines
11 KiB
C++
346 lines
11 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory-mapped bridge that connects a requestor
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* and a responder through a request and response queue.
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*/
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#ifndef __MEM_BRIDGE_HH__
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#define __MEM_BRIDGE_HH__
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#include <deque>
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#include "base/types.hh"
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#include "mem/port.hh"
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#include "params/Bridge.hh"
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#include "sim/clocked_object.hh"
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namespace gem5
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{
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/**
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* A bridge is used to interface two different crossbars (or in general a
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* memory-mapped requestor and responder), with buffering for requests and
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* responses. The bridge has a fixed delay for packets passing through
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* it and responds to a fixed set of address ranges.
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*
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* The bridge comprises a response port and a request port, that buffer
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* outgoing responses and requests respectively. Buffer space is
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* reserved when a request arrives, also reserving response space
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* before forwarding the request. If there is no space present, then
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* the bridge will delay accepting the packet until space becomes
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* available.
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*/
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class Bridge : public ClockedObject
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{
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protected:
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/**
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* A deferred packet stores a packet along with its scheduled
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* transmission time
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*/
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class DeferredPacket
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{
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public:
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const Tick tick;
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const PacketPtr pkt;
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DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
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{ }
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};
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// Forward declaration to allow the response port to have a pointer
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class BridgeRequestPort;
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/**
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* The port on the side that receives requests and sends
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* responses. The response port has a set of address ranges that it
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* is responsible for. The response port also has a buffer for the
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* responses not yet sent.
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*/
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class BridgeResponsePort : public ResponsePort
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{
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private:
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/** The bridge to which this port belongs. */
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Bridge& bridge;
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/**
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* Request port on the other side of the bridge.
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*/
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BridgeRequestPort& memSidePort;
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/** Minimum request delay though this bridge. */
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const Cycles delay;
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/** Address ranges to pass through the bridge */
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const AddrRangeList ranges;
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/**
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* Response packet queue. Response packets are held in this
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* queue for a specified delay to model the processing delay
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* of the bridge. We use a deque as we need to iterate over
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* the items for functional accesses.
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*/
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std::deque<DeferredPacket> transmitList;
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/** Counter to track the outstanding responses. */
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unsigned int outstandingResponses;
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/** If we should send a retry when space becomes available. */
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bool retryReq;
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/** Max queue size for reserved responses. */
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unsigned int respQueueLimit;
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/**
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* Upstream caches need this packet until true is returned, so
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* hold it for deletion until a subsequent call
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*/
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std::unique_ptr<Packet> pendingDelete;
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/**
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* Is this side blocked from accepting new response packets.
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*
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* @return true if the reserved space has reached the set limit
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*/
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bool respQueueFull() const;
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/**
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* Handle send event, scheduled when the packet at the head of
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* the response queue is ready to transmit (for timing
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* accesses only).
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*/
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void trySendTiming();
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/** Send event for the response queue. */
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EventFunctionWrapper sendEvent;
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public:
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/**
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* Constructor for the BridgeResponsePort.
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*
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* @param _name the port name including the owner
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* @param _bridge the structural owner
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* @param _memSidePort the request port on the other
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* side of the bridge
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* @param _delay the delay in cycles from receiving to sending
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* @param _resp_limit the size of the response queue
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* @param _ranges a number of address ranges to forward
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*/
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BridgeResponsePort(const std::string& _name, Bridge& _bridge,
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BridgeRequestPort& _memSidePort, Cycles _delay,
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int _resp_limit, std::vector<AddrRange> _ranges);
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/**
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* Queue a response packet to be sent out later and also schedule
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* a send if necessary.
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*
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* @param pkt a response to send out after a delay
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* @param when tick when response packet should be sent
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*/
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void schedTimingResp(PacketPtr pkt, Tick when);
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/**
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* Retry any stalled request that we have failed to accept at
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* an earlier point in time. This call will do nothing if no
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* request is waiting.
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*/
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void retryStalledReq();
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protected:
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/** When receiving a timing request from the peer port,
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pass it to the bridge. */
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bool recvTimingReq(PacketPtr pkt) override;
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/** When receiving a retry request from the peer port,
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pass it to the bridge. */
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void recvRespRetry() override;
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/** When receiving an Atomic request from the peer port,
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pass it to the bridge. */
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Tick recvAtomic(PacketPtr pkt) override;
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/** When receiving an Atomic backdoor request from the peer port,
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pass it to the bridge. */
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Tick recvAtomicBackdoor(
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PacketPtr pkt, MemBackdoorPtr &backdoor) override;
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/** When receiving a Functional request from the peer port,
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pass it to the bridge. */
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void recvFunctional(PacketPtr pkt) override;
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/** When receiving a Functional backdoor request from the peer port,
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pass it to the bridge. */
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void recvMemBackdoorReq(
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const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override;
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/** When receiving a address range request the peer port,
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pass it to the bridge. */
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AddrRangeList getAddrRanges() const override;
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};
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/**
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* Port on the side that forwards requests and receives
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* responses. The request port has a buffer for the requests not
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* yet sent.
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*/
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class BridgeRequestPort : public RequestPort
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{
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private:
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/** The bridge to which this port belongs. */
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Bridge& bridge;
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/**
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* The response port on the other side of the bridge.
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*/
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BridgeResponsePort& cpuSidePort;
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/** Minimum delay though this bridge. */
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const Cycles delay;
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/**
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* Request packet queue. Request packets are held in this
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* queue for a specified delay to model the processing delay
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* of the bridge. We use a deque as we need to iterate over
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* the items for functional accesses.
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*/
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std::deque<DeferredPacket> transmitList;
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/** Max queue size for request packets */
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const unsigned int reqQueueLimit;
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/**
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* Handle send event, scheduled when the packet at the head of
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* the outbound queue is ready to transmit (for timing
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* accesses only).
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*/
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void trySendTiming();
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/** Send event for the request queue. */
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EventFunctionWrapper sendEvent;
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public:
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/**
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* Constructor for the BridgeRequestPort.
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*
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* @param _name the port name including the owner
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* @param _bridge the structural owner
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* @param _cpuSidePort the response port on the other side of
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* the bridge
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* @param _delay the delay in cycles from receiving to sending
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* @param _req_limit the size of the request queue
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*/
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BridgeRequestPort(const std::string& _name, Bridge& _bridge,
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BridgeResponsePort& _cpuSidePort, Cycles _delay,
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int _req_limit);
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/**
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* Is this side blocked from accepting new request packets.
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*
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* @return true if the occupied space has reached the set limit
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*/
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bool reqQueueFull() const;
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/**
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* Queue a request packet to be sent out later and also schedule
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* a send if necessary.
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*
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* @param pkt a request to send out after a delay
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* @param when tick when response packet should be sent
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*/
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void schedTimingReq(PacketPtr pkt, Tick when);
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/**
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* Check a functional request against the packets in our
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* request queue.
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*
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* @param pkt packet to check against
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*
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* @return true if we find a match
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*/
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bool trySatisfyFunctional(PacketPtr pkt);
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protected:
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/** When receiving a timing request from the peer port,
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pass it to the bridge. */
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bool recvTimingResp(PacketPtr pkt) override;
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/** When receiving a retry request from the peer port,
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pass it to the bridge. */
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void recvReqRetry() override;
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};
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/** Response port of the bridge. */
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BridgeResponsePort cpuSidePort;
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/** Request port of the bridge. */
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BridgeRequestPort memSidePort;
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public:
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Port &getPort(const std::string &if_name,
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PortID idx=InvalidPortID) override;
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void init() override;
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typedef BridgeParams Params;
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Bridge(const Params &p);
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};
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} // namespace gem5
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#endif //__MEM_BRIDGE_HH__
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