Files
gem5/src
Yangyu Chen b0d81ec8a2 arch-riscv: fix GDB breakpoint issue for RV32 (#1470)
Since PR #1316, we use sign-extend for all address generation, including
PC, to match the ISA specification for modifiable XLEN. However, when we
set a breakpoint using remote GDB, our address is not sign-extended.
This causes the breakpoint to be set at the wrong address, as specified
in Issue #1463. This PR fixes the issue by sign-extending the address
when setting a breakpoint. This also matches the RISC-V ISA
Specification that "must sign-extend results to fill the entire widest
supported XLEN in the destination register."

Change-Id: I9b493bf8ad5b1ef45a9728bb40fc5e38250fe9c3

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
2024-08-19 10:25:39 -07:00
..
2024-08-08 12:46:10 -07:00
2024-08-14 07:16:10 -07:00