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b043dcf58ad766582aeab162fb855cc3fc95f2cf
gem5/src/mem
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Andreas Sandberg b043dcf58a gpu-compute: Fix Python/C++ object hierarchy discrepancies 
The GPUCoalescer and the Shader classes have different base classes in
C++ and Python. This causes subtle bugs in SWIG and compilation errors
for PyBind.

Change-Id: I1ddd2a8ea43f083470538ddfea891347b21d14d8
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2228
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
2017-03-07 11:50:35 +00:00
..
cache
mem: Make blkAlign a common function between all tag classes
2017-03-03 14:09:42 +00:00
probes
mem: Fix memory footprint includes
2017-02-19 05:30:31 -05:00
protocol
ruby: init MessageSizeType of SequencerMsg to Request_Control
2016-11-19 12:39:04 -05:00
ruby
gpu-compute: Fix Python/C++ object hierarchy discrepancies
2017-03-07 11:50:35 +00:00
slicc
ruby: fix and/or precedence in slicc
2017-03-01 11:58:37 +00:00
abstract_mem.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
abstract_mem.hh
cpu, mem, sim: Change how KVM maps memory
2016-08-22 11:41:05 -04:00
AbstractMemory.py
cpu, mem, sim: Change how KVM maps memory
2016-08-22 11:41:05 -04:00
addr_mapper.cc
mem: Make cache terminology easier to understand
2015-12-31 09:32:58 -05:00
addr_mapper.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
AddrMapper.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bridge.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
bridge.hh
mem: Align rules for sinking inhibited packets at the slave
2015-11-06 03:26:35 -05:00
Bridge.py
mem: Tidy up the bridge with const and additional checks
2013-06-27 05:49:49 -04:00
coherent_xbar.cc
mem: Make packet debug printing more uniform
2016-12-05 16:48:21 -05:00
coherent_xbar.hh
sim: Ensure draining is deterministic
2017-02-19 05:30:31 -05:00
comm_monitor.cc
mem, stats: fix typos in CommMonitor and Stats
2017-02-15 14:59:06 -06:00
comm_monitor.hh
mem, stats: fix typos in CommMonitor and Stats
2017-02-15 14:59:06 -06:00
CommMonitor.py
mem: Move trace functionality from the CommMonitor to a probe
2015-08-04 10:29:13 +01:00
dram_ctrl.cc
mem: fix assertion in respondEvent
2017-02-15 09:28:44 -06:00
dram_ctrl.hh
mem: Add DRAM low-power functionality
2016-10-13 19:22:11 +01:00
DRAMCtrl.py
mem: Update DRAM configuration names
2017-02-14 15:09:18 -06:00
drampower.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
drampower.hh
mem: Fix search-replace issues in DRAMPower wrapper license
2015-11-25 13:52:56 -05:00
dramsim2_wrapper.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
dramsim2_wrapper.hh
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
dramsim2.hh
mem: Unify delayed packet deletion
2015-11-06 03:26:21 -05:00
DRAMSim2.py
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
external_master.cc
misc: add a MasterId to the ExternalPort
2017-02-09 19:14:58 -05:00
external_master.hh
misc: add a MasterId to the ExternalPort
2017-02-09 19:14:58 -05:00
external_slave.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
external_slave.hh
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
ExternalMaster.py
misc: add a MasterId to the ExternalPort
2017-02-09 19:14:58 -05:00
ExternalSlave.py
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
fs_translating_port_proxy.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
fs_translating_port_proxy.hh
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
hmc_controller.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
hmc_controller.hh
mem: hmc: adds controller
2015-11-03 12:17:56 -06:00
HMCController.py
mem: hmc: adds controller
2015-11-03 12:17:56 -06:00
mem_checker_monitor.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
mem_checker_monitor.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
mem_checker.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
mem_checker.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
mem_object.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
mem_object.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
MemChecker.py
mem: Add MemChecker and MemCheckerMonitor
2014-12-23 09:31:17 -05:00
MemObject.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
multi_level_page_table_impl.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
multi_level_page_table.cc
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
multi_level_page_table.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
noncoherent_xbar.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
noncoherent_xbar.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
packet_access.hh
mem: fix bug in packet access endianness changes
2016-01-11 16:20:38 -05:00
packet_queue.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
packet_queue.hh
mem: Order packet queue only on matching addresses
2015-11-06 03:26:38 -05:00
packet.cc
mem: Make packet debug printing more uniform
2016-12-05 16:48:21 -05:00
packet.hh
mem: Assert that the responderHadWritable is set only once
2016-12-05 16:48:24 -05:00
page_table.cc
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
page_table.hh
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
physical.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
physical.hh
cpu, mem, sim: Change how KVM maps memory
2016-08-22 11:41:05 -04:00
port_proxy.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
port_proxy.hh
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
port.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
port.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
qport.hh
mem: Enforce insertion order on the cache response path
2015-11-06 03:26:37 -05:00
request.hh
mem: Remove threadId from memory request class
2016-04-07 09:30:20 -05:00
SConscript
mem: hmc: serial link model
2015-11-03 12:17:57 -06:00
se_translating_port_proxy.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
se_translating_port_proxy.hh
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
serial_link.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
serial_link.hh
mem: different HMC configuration
2016-07-01 09:45:21 -05:00
SerialLink.py
mem: different HMC configuration
2016-07-01 09:45:21 -05:00
simple_mem.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
simple_mem.hh
mem: Use the packet delays and do not just zero them out
2015-11-06 03:26:36 -05:00
SimpleMemory.py
mem: Add an internal packet queue in SimpleMemory
2013-08-19 03:52:25 -04:00
snoop_filter.cc
mem: Don't use hasSharers in the snoopFilter for memory responses
2016-12-05 16:48:26 -05:00
snoop_filter.hh
mem: Add support for secure packets in the snoop filter
2016-08-12 14:11:45 +01:00
stack_dist_calc.cc
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
stack_dist_calc.hh
mem: Redesign the stack distance calculator as a probe
2015-08-04 10:29:13 +01:00
tport.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
tport.hh
mem: Unify delayed packet deletion
2015-11-06 03:26:21 -05:00
xbar.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
xbar.hh
mem: Make the BaseXBar public to not confuse Python wrappers
2016-12-19 16:25:40 +00:00
XBar.py
mem: Add snoop filter to SystemXBar by default
2016-08-12 14:11:45 +01:00