b01b455537
Gem5 Hardware Transactional Memory (HTM) Here we provide a brief note describing HTM support in Gem5 at a high level. HTM is an architectural feature that enables speculative concurrency in a shared-memory system; groups of instructions known as transactions are executed as an atomic unit. The system allows that transactions be executed concurrently but intervenes if a transaction's atomicity/isolation is jeapordised and takes corrective action. In this implementation, corrective active explicitely means rolling back a thread's architectural state and reverting any memory updates to a point just before the transaction began. This HTM implementation relies on-- (1) A checkpointing mechanism for architectural register state. (2) Buffering speculative memory updates. This patch is focusing on the definition of the HTM checkpoint (1) The checkpointing mechanism is architecture dependent. Each ISA leveraging HTM support can define a class HTMCheckpoint inhereting from the generic one (GenericISA::HTMCheckpoint). Those will need to save/restore the architectural state by overriding the virtual HTMCheckpoint::save (when starting a transaction) and HTMCheckpoint::restore (when aborting a transaction). Instances of this class live in O3's ThreadState and Atomic's SimpleThread. It is up to the ISA to populate this instance when executing an instruction that begins a new transaction. JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Icd8d1913d23652d78fe89e930ab1e302eb52363d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30314 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
125 lines
4.0 KiB
Python
125 lines
4.0 KiB
Python
# -*- mode:python -*-
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#
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# Copyright (c) 2018-2019 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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SimObject('CommMonitor.py')
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Source('comm_monitor.cc')
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SimObject('AbstractMemory.py')
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SimObject('AddrMapper.py')
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SimObject('Bridge.py')
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SimObject('DRAMCtrl.py')
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SimObject('ExternalMaster.py')
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SimObject('ExternalSlave.py')
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SimObject('MemObject.py')
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SimObject('SimpleMemory.py')
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SimObject('XBar.py')
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SimObject('HMCController.py')
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SimObject('SerialLink.py')
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SimObject('MemDelay.py')
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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Source('bridge.cc')
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Source('coherent_xbar.cc')
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Source('drampower.cc')
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Source('dram_ctrl.cc')
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Source('external_master.cc')
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Source('external_slave.cc')
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Source('noncoherent_xbar.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('packet_queue.cc')
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Source('port_proxy.cc')
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Source('physical.cc')
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Source('simple_mem.cc')
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Source('snoop_filter.cc')
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Source('stack_dist_calc.cc')
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Source('token_port.cc')
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Source('tport.cc')
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Source('xbar.cc')
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Source('hmc_controller.cc')
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Source('htm.cc')
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Source('serial_link.cc')
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Source('mem_delay.cc')
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if env['TARGET_ISA'] != 'null':
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Source('translating_port_proxy.cc')
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Source('se_translating_port_proxy.cc')
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Source('page_table.cc')
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if env['HAVE_DRAMSIM']:
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SimObject('DRAMSim2.py')
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Source('dramsim2_wrapper.cc')
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Source('dramsim2.cc')
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SimObject('MemChecker.py')
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Source('mem_checker.cc')
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Source('mem_checker_monitor.cc')
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DebugFlag('AddrRanges')
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DebugFlag('BaseXBar')
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DebugFlag('CoherentXBar')
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DebugFlag('NoncoherentXBar')
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DebugFlag('SnoopFilter')
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CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
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'SnoopFilter'])
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DebugFlag('Bridge')
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DebugFlag('CommMonitor')
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DebugFlag('DRAM')
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DebugFlag('DRAMPower')
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DebugFlag('DRAMState')
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DebugFlag('ExternalPort')
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DebugFlag('LLSC')
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DebugFlag('MMU')
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DebugFlag('MemoryAccess')
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DebugFlag('PacketQueue')
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DebugFlag('StackDist')
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DebugFlag("DRAMSim2")
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DebugFlag('HMCController')
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DebugFlag('SerialLink')
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DebugFlag('TokenPort')
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DebugFlag("MemChecker")
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DebugFlag("MemCheckerMonitor")
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DebugFlag("QOS")
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