This patches decouples the prefetchers from the cache implementation as the first step to allow using the classic prefetchers with ruby caches. The prefetchers that need do cache lookups can do so using the accessor object provided when the probes are notified. This may also facilitate connecting the same prefetcher to multiple caches. Related JIRA: https://gem5.atlassian.net/browse/GEM5-457 https://gem5.atlassian.net/browse/GEM5-1112 Change-Id: I4fee1a3613ae009fabf45d7b747e4582cad315ef Signed-off-by: Tiago Mück <tiago.muck@arm.com>
211 lines
6.8 KiB
C++
211 lines
6.8 KiB
C++
/*
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* Copyright (c) 2018 Inria
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Stride Prefetcher template instantiations.
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*/
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#include "mem/cache/prefetch/stride.hh"
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#include <cassert>
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#include "base/intmath.hh"
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#include "base/logging.hh"
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#include "base/random.hh"
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#include "base/trace.hh"
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#include "debug/HWPrefetch.hh"
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#include "mem/cache/prefetch/associative_set_impl.hh"
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#include "mem/cache/replacement_policies/base.hh"
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#include "params/StridePrefetcher.hh"
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namespace gem5
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{
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namespace prefetch
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{
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Stride::StrideEntry::StrideEntry(const SatCounter8& init_confidence)
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: TaggedEntry(), confidence(init_confidence)
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{
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invalidate();
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}
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void
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Stride::StrideEntry::invalidate()
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{
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TaggedEntry::invalidate();
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lastAddr = 0;
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stride = 0;
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confidence.reset();
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}
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Stride::Stride(const StridePrefetcherParams &p)
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: Queued(p),
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initConfidence(p.confidence_counter_bits, p.initial_confidence),
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threshConf(p.confidence_threshold/100.0),
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useRequestorId(p.use_requestor_id),
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degree(p.degree),
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pcTableInfo(p.table_assoc, p.table_entries, p.table_indexing_policy,
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p.table_replacement_policy)
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{
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}
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Stride::PCTable*
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Stride::findTable(int context)
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{
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// Check if table for given context exists
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auto it = pcTables.find(context);
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if (it != pcTables.end())
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return &it->second;
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// If table does not exist yet, create one
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return allocateNewContext(context);
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}
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Stride::PCTable*
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Stride::allocateNewContext(int context)
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{
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// Create new table
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auto insertion_result = pcTables.insert(std::make_pair(context,
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PCTable(pcTableInfo.assoc, pcTableInfo.numEntries,
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pcTableInfo.indexingPolicy, pcTableInfo.replacementPolicy,
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StrideEntry(initConfidence))));
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DPRINTF(HWPrefetch, "Adding context %i with stride entries\n", context);
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// Get iterator to new pc table, and then return a pointer to the new table
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return &(insertion_result.first->second);
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}
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void
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Stride::calculatePrefetch(const PrefetchInfo &pfi,
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std::vector<AddrPriority> &addresses,
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const CacheAccessor &cache)
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{
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if (!pfi.hasPC()) {
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DPRINTF(HWPrefetch, "Ignoring request with no PC.\n");
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return;
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}
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// Get required packet info
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Addr pf_addr = pfi.getAddr();
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Addr pc = pfi.getPC();
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bool is_secure = pfi.isSecure();
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RequestorID requestor_id = useRequestorId ? pfi.getRequestorId() : 0;
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// Get corresponding pc table
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PCTable* pcTable = findTable(requestor_id);
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// Search for entry in the pc table
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StrideEntry *entry = pcTable->findEntry(pc, is_secure);
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if (entry != nullptr) {
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pcTable->accessEntry(entry);
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// Hit in table
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int new_stride = pf_addr - entry->lastAddr;
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bool stride_match = (new_stride == entry->stride);
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// Adjust confidence for stride entry
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if (stride_match && new_stride != 0) {
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entry->confidence++;
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} else {
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entry->confidence--;
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// If confidence has dropped below the threshold, train new stride
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if (entry->confidence.calcSaturation() < threshConf) {
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entry->stride = new_stride;
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}
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}
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DPRINTF(HWPrefetch, "Hit: PC %x pkt_addr %x (%s) stride %d (%s), "
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"conf %d\n", pc, pf_addr, is_secure ? "s" : "ns",
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new_stride, stride_match ? "match" : "change",
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(int)entry->confidence);
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entry->lastAddr = pf_addr;
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// Abort prefetch generation if below confidence threshold
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if (entry->confidence.calcSaturation() < threshConf) {
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return;
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}
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// Generate up to degree prefetches
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for (int d = 1; d <= degree; d++) {
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// Round strides up to atleast 1 cacheline
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int prefetch_stride = new_stride;
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if (abs(new_stride) < blkSize) {
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prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
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}
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Addr new_addr = pf_addr + d * prefetch_stride;
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addresses.push_back(AddrPriority(new_addr, 0));
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}
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} else {
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// Miss in table
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DPRINTF(HWPrefetch, "Miss: PC %x pkt_addr %x (%s)\n", pc, pf_addr,
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is_secure ? "s" : "ns");
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StrideEntry* entry = pcTable->findVictim(pc);
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// Insert new entry's data
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entry->lastAddr = pf_addr;
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pcTable->insertEntry(pc, is_secure, entry);
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}
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}
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uint32_t
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StridePrefetcherHashedSetAssociative::extractSet(const Addr pc) const
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{
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const Addr hash1 = pc >> 1;
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const Addr hash2 = hash1 >> tagShift;
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return (hash1 ^ hash2) & setMask;
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}
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Addr
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StridePrefetcherHashedSetAssociative::extractTag(const Addr addr) const
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{
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return addr;
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}
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} // namespace prefetch
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} // namespace gem5
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