cdcc55a6a8
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
73 lines
3.5 KiB
Python
73 lines
3.5 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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from m5.params import *
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from m5.SimObject import SimObject
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# An address mapper changes the packet addresses in going from the
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# slave port side of the mapper to the master port side. When the
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# slave port is queried for the address ranges, it also performs the
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# necessary range updates. Note that snoop requests that travel from
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# the master port (i.e. the memory side) to the slave port are
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# currently not modified.
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class AddrMapper(SimObject):
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type = 'AddrMapper'
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cxx_header = 'mem/addr_mapper.hh'
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abstract = True
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# one port in each direction
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master = MasterPort("Master port")
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slave = SlavePort("Slave port")
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# Range address mapper that maps a set of original ranges to a set of
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# remapped ranges, where a specific range is of the same size
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# (original and remapped), only with an offset.
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class RangeAddrMapper(AddrMapper):
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type = 'RangeAddrMapper'
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cxx_header = 'mem/addr_mapper.hh'
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# These two vectors should be the exact same length and each range
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# should be the exact same size. Each range in original_ranges is
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# mapped to the corresponding element in the remapped_ranges. Note
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# that the same range can occur multiple times in the remapped
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# ranges for address aliasing.
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original_ranges = VectorParam.AddrRange(
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"Ranges of memory that should me remapped")
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remapped_ranges = VectorParam.AddrRange(
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"Ranges of memory that are being mapped to")
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