As X86 and RISCV are relying on a Table Walker cache, we change their stdlib configs to use the newly defined PrivateL1PrivateL2WalkCacheHierarchy Change-Id: I63c3f70a9daa3b2c7a8306e51af8065bf1bea92b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>