823b5a6eb8
Currently gem5 assumes that there is only one command processor (CP) which contains the PM4 packet processor. Some GPU devices have multiple CPs which the driver tests individually during POST if they are used or not. Therefore, these additional CPs need to be supported. This commit allows for multiple PM4 packet processors which represent multiple CPs. Each of these processors will have its own independent MMIO address range. To more easily support ranges, the MMIO addresses now use AddrRange to index a PM4 packet processor instead of the hard-coded constexpr MMIO start and size pairs. By default only one PM4 packet processor is created, meaning the functionality of the simulation is unchanged for devices currently supported in gem5. Change-Id: I977f4fd3a169ef4a78671a4fb58c8ea0e19bf52c
71 lines
3.7 KiB
C++
71 lines
3.7 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_AMDGPU_PM4_MMIO_HH__
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#define __DEV_AMDGPU_PM4_MMIO_HH__
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namespace gem5
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{
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#define mmCP_RB0_BASE 0x040
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#define mmCP_RB0_CNTL 0x041
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#define mmCP_RB_WPTR_POLL_ADDR_LO 0x046
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#define mmCP_RB_WPTR_POLL_ADDR_HI 0x047
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#define mmCP_RB_VMID 0x051
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#define mmCP_RB0_RPTR_ADDR 0x043
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#define mmCP_RB0_RPTR_ADDR_HI 0x044
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#define mmCP_RB0_WPTR 0x054
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#define mmCP_RB0_WPTR_HI 0x055
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#define mmCP_RB_DOORBELL_CONTROL 0x059
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#define mmCP_RB_DOORBELL_RANGE_LOWER 0x05a
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#define mmCP_RB_DOORBELL_RANGE_UPPER 0x05b
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#define mmCP_RB0_BASE_HI 0x0b1
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#define mmCP_HQD_ACTIVE 0x247
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#define mmCP_HQD_VMID 0x248
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#define mmCP_HQD_PQ_BASE 0x24d
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#define mmCP_HQD_PQ_BASE_HI 0x24e
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#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x254
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#define mmCP_HQD_PQ_RPTR 0x24f
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#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x250
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#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x251
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#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x252
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#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x253
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#define mmCP_HQD_PQ_CONTROL 0x256
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#define mmCP_HQD_IB_CONTROL 0x25a
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#define mmCP_HQD_PQ_WPTR_LO 0x27b
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#define mmCP_HQD_PQ_WPTR_HI 0x27c
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} // namespace gem5
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#endif // __DEV_AMDGPU_PM4_MMIO_HH__
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