63caa780c2
Replace instances of "GCN3" with Vega. Remove gfx801 and gfx803. Rename FIJI to Vega and Carrizo to Raven. Using misc since there is not enough room to fit all the tags. Change-Id: Ibafc939d49a69be9068107a906e878408c7a5891
75 lines
2.5 KiB
C++
75 lines
2.5 KiB
C++
/*
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* Copyright (c) 2022 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_GPU_HWREG_DEFINES_H__
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#define __DEV_GPU_HWREG_DEFINES_H__
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/*
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* This enum is adapted from the offsets seen by LLVM:
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*
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* https://github.com/llvm/llvm-project/blob/release/14.x/llvm/lib/
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* Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp#L58
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*/
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namespace gem5
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{
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/*
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* Further descriptions can be found in the "Hardware Register Values" table
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* in any of the Vega, CDNA, or RDNA ISA manuals.
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*/
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enum amdgpu_hwreg
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{
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HW_REG_MODE = 0x1,
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HW_REG_STATUS = 0x2,
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HW_REG_TRAPSTS = 0x3,
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HW_REG_HW_ID = 0x4,
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HW_REG_GPR_ALLOC = 0x5,
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HW_REG_LDS_ALLOC = 0x6,
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HW_REG_IB_STS = 0x7,
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HW_REG_SH_MEM_BASES = 0xf,
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HW_REG_TBA_LO = 0x10,
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HW_REG_TBA_HI = 0x11,
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HW_REG_TMA_LO = 0x12,
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HW_REG_TMA_HI = 0x13,
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HW_REG_FLAT_SCR_LO = 0x14,
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HW_REG_FLAT_SCR_HI = 0x15,
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HW_REG_XNACK_MASK = 0x16,
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HW_REG_HW_ID1 = 0x17,
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HW_REG_HW_ID2 = 0x18,
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HW_REG_POPS_PACKER = 0x19,
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HW_REG_SHADER_CYCLES = 0x1d,
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};
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} // namespace gem5
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#endif // __DEV_GPU_HWREG_DEFINES_H__
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