39153cd234
PCIe can read/write to any 32-bit address using the PCI index/index2 registers as an address and then reading/writing the corresponding data/data2 register. This commit adds this functionality and removes one magic value being written to support GPU POST. This feature is disabled for Vega10 which relies on an MMIO trace for too many values to implement in the MMIO interface. Change-Id: Iacfdd1294a7652fc3e60304b57df536d318c847b
238 lines
9.1 KiB
C++
238 lines
9.1 KiB
C++
/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/amdgpu/amdgpu_nbio.hh"
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#include "debug/AMDGPUDevice.hh"
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#include "dev/amdgpu/amdgpu_device.hh"
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#include "mem/packet_access.hh"
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namespace gem5
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{
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AMDGPUNbio::AMDGPUNbio()
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{
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// All read-before-write MMIOs go here
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triggered_reads[AMDGPU_MP0_SMN_C2PMSG_64] = 0x80000000;
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}
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void
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AMDGPUNbio::setGPUDevice(AMDGPUDevice *gpu_device)
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{
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gpuDevice = gpu_device;
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}
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void
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AMDGPUNbio::readMMIO(PacketPtr pkt, Addr offset)
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{
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// For Vega10 we rely on the golden values in an MMIO trace. Return
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// immediately as to not clobber those values.
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if (gpuDevice->getGfxVersion() == GfxVersion::gfx900) {
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if (offset == AMDGPU_PCIE_DATA || offset == AMDGPU_PCIE_DATA2) {
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return;
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}
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}
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switch (offset) {
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// PCIE_DATA, PCIE_DATA2, PCIE_INDEX, and PCIE_INDEX2 handle "indirect
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// "register reads/writes from the driver. This provides a way to read
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// any register by providing a 32-bit address to one of the two INDEX
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// registers and then reading the corresponding DATA register. See:
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// https://github.com/ROCm/ROCK-Kernel-Driver/blob/roc-6.0.x/drivers/
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// gpu/drm/amd/amdgpu/amdgpu_device.c#L459
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case AMDGPU_PCIE_DATA:
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{
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uint32_t value = gpuDevice->getRegVal(pcie_index_reg);
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DPRINTF(AMDGPUDevice, "Read PCIe index %lx data %x\n",
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pcie_index_reg, value);
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pkt->setLE<uint32_t>(value);
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}
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break;
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case AMDGPU_PCIE_DATA2:
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{
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uint32_t value = gpuDevice->getRegVal(pcie_index2_reg);
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DPRINTF(AMDGPUDevice, "Read PCIe index2 %lx data2 %x\n",
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pcie_index2_reg, value);
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pkt->setLE<uint32_t>(value);
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}
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break;
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case AMDGPU_PCIE_INDEX:
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pkt->setLE<uint32_t>(pcie_index_reg);
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break;
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case AMDGPU_PCIE_INDEX2:
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pkt->setLE<uint32_t>(pcie_index2_reg);
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break;
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case AMDGPU_MM_DATA:
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pkt->setLE<uint32_t>(gpuDevice->getRegVal(mm_index_reg));
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break;
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case VEGA10_INV_ENG17_ACK1:
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case VEGA10_INV_ENG17_ACK2:
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case MI100_INV_ENG17_ACK2:
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case MI100_INV_ENG17_ACK3:
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case MI200_INV_ENG17_ACK2:
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pkt->setLE<uint32_t>(0x10001);
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break;
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case VEGA10_INV_ENG17_SEM1:
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case VEGA10_INV_ENG17_SEM2:
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case MI100_INV_ENG17_SEM2:
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case MI100_INV_ENG17_SEM3:
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case MI200_INV_ENG17_SEM2:
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pkt->setLE<uint32_t>(0x1);
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break;
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// PSP responds with bit 31 set when ready
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case AMDGPU_MP0_SMN_C2PMSG_35:
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pkt->setLE<uint32_t>(0x80000000);
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break;
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case AMDGPU_MP1_SMN_C2PMSG_90:
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pkt->setLE<uint32_t>(0x1);
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break;
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default:
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if (triggered_reads.count(offset)) {
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DPRINTF(AMDGPUDevice, "Found triggered read for %#x\n", offset);
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pkt->setLE<uint32_t>(triggered_reads[offset]);
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} else if (regs.count(offset)) {
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DPRINTF(AMDGPUDevice, "Returning value of unknown MMIO offset "
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"%x: %x\n", offset, regs[offset]);
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pkt->setLE<uint32_t>(regs[offset]);
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} else {
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DPRINTF(AMDGPUDevice, "NBIO Unknown MMIO %#x (%#x)\n", offset,
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pkt->getAddr());
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}
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break;
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}
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}
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void
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AMDGPUNbio::writeMMIO(PacketPtr pkt, Addr offset)
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{
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if (offset == AMDGPU_MM_INDEX) {
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assert(pkt->getSize() == 4);
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mm_index_reg = insertBits(mm_index_reg, 31, 0,
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pkt->getLE<uint32_t>());
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} else if (offset == AMDGPU_MM_INDEX_HI) {
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assert(pkt->getSize() == 4);
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mm_index_reg = insertBits(mm_index_reg, 63, 32,
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pkt->getLE<uint32_t>());
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} else if (offset == AMDGPU_MM_DATA) {
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DPRINTF(AMDGPUDevice, "MM write to reg %#lx data %#lx\n",
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mm_index_reg, pkt->getLE<uint32_t>());
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gpuDevice->setRegVal(AMDGPU_MM_DATA, pkt->getLE<uint32_t>());
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// PCIE_DATA, PCIE_DATA2, PCIE_INDEX, and PCIE_INDEX2 handle "indirect
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// "register reads/writes from the driver. This provides a way to read
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// any register by providing a 32-bit address to one of the two INDEX
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// registers and then reading the corresponding DATA register. See:
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// https://github.com/ROCm/ROCK-Kernel-Driver/blob/roc-6.0.x/drivers/
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// gpu/drm/amd/amdgpu/amdgpu_device.c#L459
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} else if (offset == AMDGPU_PCIE_INDEX) {
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assert(pkt->getSize() == 4);
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pcie_index_reg = pkt->getLE<uint32_t>();
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} else if (offset == AMDGPU_PCIE_DATA) {
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assert(pkt->getSize() == 4);
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gpuDevice->setRegVal(pcie_index_reg, pkt->getLE<uint32_t>());
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} else if (offset == AMDGPU_PCIE_INDEX2) {
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assert(pkt->getSize() == 4);
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pcie_index2_reg = pkt->getLE<uint32_t>();
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} else if (offset == AMDGPU_PCIE_DATA2) {
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assert(pkt->getSize() == 4);
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gpuDevice->setRegVal(pcie_index2_reg, pkt->getLE<uint32_t>());
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} else if (offset == AMDGPU_MP0_SMN_C2PMSG_35) {
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// See psp_v3_1_bootloader_load_sos in amdgpu driver code.
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if (pkt->getLE<uint32_t>() == 0x10000) {
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triggered_reads[AMDGPU_MP0_SMN_C2PMSG_81] = 0xdf40b31;
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}
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} else if (offset == AMDGPU_MP0_SMN_C2PMSG_64) {
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triggered_reads[AMDGPU_MP0_SMN_C2PMSG_64] =
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0x80000000 + pkt->getLE<uint32_t>();
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} else if (offset == AMDGPU_MP0_SMN_C2PMSG_69) {
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// PSP ring low addr
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psp_ring = insertBits(psp_ring, 31, 0, pkt->getLE<uint32_t>());
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psp_ring_listen_addr = psp_ring
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- gpuDevice->getVM().getSysAddrRangeLow() + 0xc;
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} else if (offset == AMDGPU_MP0_SMN_C2PMSG_70) {
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// PSP ring high addr
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psp_ring = insertBits(psp_ring, 63, 32, pkt->getLE<uint32_t>());
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psp_ring_listen_addr = psp_ring
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- gpuDevice->getVM().getSysAddrRangeLow() + 0xc;
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} else if (offset == AMDGPU_MP0_SMN_C2PMSG_71) {
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// PSP ring size
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psp_ring_size = pkt->getLE<uint32_t>();
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} else {
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// Fallback to a map of register values. This was previously in the
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// AMDGPUDevice, however that short-circuited some reads from other
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// IP blocks. Since this is an end point IP block it is safer to use
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// here.
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regs[offset] = pkt->getLE<uint32_t>();
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DPRINTF(AMDGPUDevice, "Writing value of unknown MMIO offset "
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"%x: %x\n", offset, regs[offset]);
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}
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}
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bool
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AMDGPUNbio::readFrame(PacketPtr pkt, Addr offset)
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{
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if (offset == psp_ring_dev_addr) {
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psp_ring_value++;
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pkt->setUintX(psp_ring_value, ByteOrder::little);
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return true;
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}
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return false;
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}
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void
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AMDGPUNbio::writeFrame(PacketPtr pkt, Addr offset)
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{
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if (offset == psp_ring_listen_addr) {
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DPRINTF(AMDGPUDevice, "Saw psp_ring_listen_addr with size %ld value "
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"%ld\n", pkt->getSize(), pkt->getUintX(ByteOrder::little));
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/*
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* In ROCm versions 4.x this packet is a 4 byte value. In ROCm 5.x
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* the packet is 8 bytes and mapped as a system address which needs
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* to be subtracted out to get the framebuffer address.
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*/
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if (pkt->getSize() == 4) {
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psp_ring_dev_addr = pkt->getLE<uint32_t>();
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} else if (pkt->getSize() == 8) {
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psp_ring_dev_addr = pkt->getUintX(ByteOrder::little)
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- gpuDevice->getVM().getSysAddrRangeLow();
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} else {
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panic("Invalid write size to psp_ring_listen_addr\n");
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}
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DPRINTF(AMDGPUDevice, "Setting PSP ring device address to %#lx\n",
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psp_ring_dev_addr);
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}
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}
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} // namespace gem5
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