Steve Reinhardt 62c08a75ad Make default PhysicalMemory latency slightly more realistic. ...

Also update stats to reflect change.

2008-08-03 18:13:29 -04:00

..

cache

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

bridge.hh

Don't FastAlloc MSHRs since we don't allocate them on the fly.

2008-03-24 01:08:02 -04:00

Bridge.py

DMA: Add IOCache and fix bus bridge to optionally only send requests one

2007-08-10 16:14:01 -04:00

bus.cc

Add missing newlines to Bus DPRINTFs.

2008-07-15 14:38:51 -04:00

bus.hh

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

Bus.py

Bus: Fix the bus timing to be more realistic.

2008-02-26 02:20:08 -05:00

dram.cc

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

dram.hh

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mem_object.cc

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

mem_object.hh

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

packet_access.hh

Make byteswap work correctly on Twin??_t types.

2007-03-07 17:46:04 +00:00

packet.cc

Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.

2008-07-15 14:38:51 -04:00

packet.hh

Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.

2008-07-15 14:38:51 -04:00

page_table.cc

Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.

2007-11-14 23:42:08 -05:00

page_table.hh

TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.

2007-10-25 19:04:44 -07:00

physical.cc

physmem: Add a null option to physical memory so it doesn't store data.

2008-06-15 21:39:29 -07:00

physical.hh

PhysicalMemory: Add parameter for variance in memory delay.

2008-04-10 14:44:52 -04:00

PhysicalMemory.py

Make default PhysicalMemory latency slightly more realistic.

2008-08-03 18:13:29 -04:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

port.hh

Backed out changeset 94a7bb476fca: caused memory leak.

2008-06-28 13:19:38 -04:00

request.hh

MemReq: Add option to reset the time on a request.

2008-06-14 19:39:01 -07:00

SConscript

SCons: add comments to SConscript documenting bug workaround

2008-04-10 15:38:10 -04:00

tport.cc

Get rid of bogus bus assertion.

2008-06-13 01:33:49 -04:00

tport.hh

memory system: fix functional access bug.

2007-07-29 20:17:03 -07:00

translating_port.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

translating_port.hh

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

vport.cc

Remove delVirtPort() and make getVirtPort() only return cached version.

2008-07-01 10:25:07 -04:00

vport.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00