ab3d37d398
instead of having one cache-unit class be responsible for both data and code accesses, separate code that is just for fetch in it's own derived class off the original base class. This makes the code easier to manage as well as handle future cases of special fetch handling
92 lines
3.7 KiB
Python
92 lines
3.7 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2007 MIPS Technologies, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Korey Sewell
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Import('*')
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if 'InOrderCPU' in env['CPU_MODELS']:
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SimObject('InOrderCPU.py')
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SimObject('InOrderTrace.py')
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TraceFlag('ResReqCount')
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TraceFlag('InOrderStage')
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TraceFlag('InOrderStall')
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TraceFlag('InOrderCPU')
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TraceFlag('RegDepMap')
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TraceFlag('InOrderDynInst')
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TraceFlag('Resource')
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TraceFlag('InOrderAGEN')
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TraceFlag('InOrderFetchSeq')
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TraceFlag('InOrderTLB')
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TraceFlag('InOrderCachePort')
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TraceFlag('InOrderBPred')
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TraceFlag('InOrderDecode')
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TraceFlag('InOrderExecute')
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TraceFlag('InOrderInstBuffer')
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TraceFlag('InOrderUseDef')
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TraceFlag('InOrderMDU')
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TraceFlag('InOrderGraduation')
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TraceFlag('ThreadModel')
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TraceFlag('RefCount')
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TraceFlag('AddrDep')
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CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
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'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
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'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
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'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
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'ThreadModel', 'AddrDep'])
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Source('pipeline_traits.cc')
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Source('inorder_dyn_inst.cc')
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Source('inorder_cpu_builder.cc')
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Source('inorder_trace.cc')
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Source('pipeline_stage.cc')
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Source('first_stage.cc')
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Source('resource.cc')
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Source('resources/agen_unit.cc')
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Source('resources/execution_unit.cc')
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Source('resources/bpred_unit.cc')
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Source('resources/branch_predictor.cc')
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Source('resources/cache_unit.cc')
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Source('resources/fetch_unit.cc')
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Source('resources/use_def.cc')
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Source('resources/decode_unit.cc')
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Source('resources/inst_buffer.cc')
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Source('resources/graduation_unit.cc')
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Source('resources/fetch_seq_unit.cc')
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Source('resources/mult_div_unit.cc')
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Source('resource_pool.cc')
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Source('resource_sked.cc')
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Source('reg_dep_map.cc')
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Source('thread_state.cc')
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Source('thread_context.cc')
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Source('cpu.cc')
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