89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
35 lines
3.0 KiB
Plaintext
35 lines
3.0 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 122377 # Simulator instruction rate (inst/s)
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host_mem_usage 192524 # Number of bytes of host memory used
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host_seconds 0.05 # Real time elapsed on the host
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host_tick_rate 61135620 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6404 # Number of instructions simulated
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 3215000 # Number of ticks simulated
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system.cpu.dtb.accesses 2060 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 2050 # DTB hits
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system.cpu.dtb.misses 10 # DTB misses
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system.cpu.dtb.read_accesses 1192 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 1185 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.write_accesses 868 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 865 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 6431 # ITB accesses
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system.cpu.itb.acv 0 # ITB acv
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system.cpu.itb.hits 6414 # ITB hits
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system.cpu.itb.misses 17 # ITB misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 6431 # number of cpu cycles simulated
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system.cpu.num_insts 6404 # Number of instructions executed
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system.cpu.num_refs 2060 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
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---------- End Simulation Statistics ----------
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