Nilay Vaish 390cfc7be9 Config: Change the way options are added ...

I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.

2012-03-28 11:01:53 -05:00

..

inorder-timing.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

memtest-ruby.py

Config: Change the way options are added

2012-03-28 11:01:53 -05:00

memtest.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

o3-timing-checker.py

CheckerCPU: Make some basic regression tests for CheckerCPU

2012-03-09 09:59:28 -05:00

o3-timing-mp-ruby.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

o3-timing-mp.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

o3-timing-ruby.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

o3-timing.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

pc-o3-timing.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

pc-simple-atomic.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

pc-simple-timing.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-o3-checker.py

CheckerCPU: Make some basic regression tests for CheckerCPU

2012-03-09 09:59:28 -05:00

realview-o3-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-o3.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-simple-atomic-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-simple-atomic.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-simple-timing-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

realview-simple-timing.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

rubytest-ruby.py

Config: Change the way options are added

2012-03-28 11:01:53 -05:00

simple-atomic-dummychecker.py

CheckerCPU: Make some basic regression tests for CheckerCPU

2012-03-09 09:59:28 -05:00

simple-atomic-mp-ruby.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

simple-atomic-mp.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

simple-atomic.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

simple-timing-mp-ruby.py

Config: Change the way options are added

2012-03-28 11:01:53 -05:00

simple-timing-mp.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

simple-timing-ruby.py

Config: Change the way options are added

2012-03-28 11:01:53 -05:00

simple-timing.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00

t1000-simple-atomic.py

Fix the SPARC fs regression by adding a call to createInterruptController.

2012-03-08 02:10:03 -08:00

tsunami-inorder.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-o3-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-o3.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-simple-atomic-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-simple-atomic.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-simple-timing-dual.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

tsunami-simple-timing.py

cache: Allow main memory to be at disjoint address ranges.

2012-03-09 09:59:25 -05:00

twosys-tsunami-simple-atomic.py

CPU: Check that the interrupt controller is created when needed

2012-03-02 09:21:48 -05:00