a8447b7fc0
The Vega ISA's s_memtime instruction is used to obtain a cycle value from the GPU. Previously, this was implemented to obtain the cycle count when the memtime instruction reached the execute stage of the GPU pipeline. However, from microbenchmarking we have found that this under reports the latency for memtime instructions relative to real hardware. Thus, we changed its behavior to go through the scalar memory pipeline and obtain a latency value from the the SQC (L1 I$). This mirrors the suggestion of the AMD Vega ISA manual that s_memtime should be treated like a s_load_dwordx2. The default latency was set based on microbenchmarking. Change-Id: I5e251dde28c06fe1c492aea4abf9f34f05784420
263 lines
7.7 KiB
Python
263 lines
7.7 KiB
Python
# Copyright (c) 2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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def addAmdGPUOptions(parser):
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parser.add_argument(
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"-u",
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"--num-compute-units",
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type=int,
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default=4,
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help="number of GPU compute units",
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),
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parser.add_argument(
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"--num-cp",
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type=int,
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default=0,
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help="Number of GPU Command Processors (CP)",
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)
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# not super important now, but to avoid putting the number 4 everywhere,
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# make it an option/knob
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parser.add_argument(
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"--cu-per-sqc",
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type=int,
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default=4,
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help="number of CUs sharing an SQC (icache, and thus icache TLB)",
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)
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parser.add_argument(
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"--cu-per-scalar-cache",
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type=int,
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default=4,
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help="Number of CUs sharing a scalar cache",
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)
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parser.add_argument(
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"--simds-per-cu", type=int, default=4, help="SIMD units per CU"
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)
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parser.add_argument(
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"--cu-per-sa",
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type=int,
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default=4,
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help="Number of CUs per shader array. This must be a"
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" multiple of options.cu-per-sqc and "
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" options.cu-per-scalar",
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)
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parser.add_argument(
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"--sa-per-complex",
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type=int,
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default=1,
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help="Number of shader arrays per complex",
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)
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parser.add_argument(
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"--num-gpu-complexes",
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type=int,
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default=1,
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help="Number of GPU complexes",
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)
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parser.add_argument(
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"--wf-size", type=int, default=64, help="Wavefront size(in workitems)"
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)
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parser.add_argument(
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"--sp-bypass-path-length",
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type=int,
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default=4,
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help="Number of stages of bypass path in vector ALU "
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"for Single Precision ops",
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)
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parser.add_argument(
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"--dp-bypass-path-length",
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type=int,
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default=4,
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help="Number of stages of bypass path in vector ALU "
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"for Double Precision ops",
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)
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# issue period per SIMD unit: number of cycles before issuing another vector
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parser.add_argument(
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"--issue-period",
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type=int,
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default=4,
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help="Number of cycles per vector instruction issue period",
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)
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parser.add_argument(
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"--glbmem-wr-bus-width",
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type=int,
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default=32,
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help="VGPR to Coalescer (Global Memory) data bus width in bytes",
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)
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parser.add_argument(
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"--glbmem-rd-bus-width",
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type=int,
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default=32,
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help="Coalescer to VGPR (Global Memory) data bus width in bytes",
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)
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# Currently we only support 1 local memory pipe
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parser.add_argument(
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"--shr-mem-pipes-per-cu",
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type=int,
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default=1,
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help="Number of Shared Memory pipelines per CU",
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)
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# Currently we only support 1 global memory pipe
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parser.add_argument(
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"--glb-mem-pipes-per-cu",
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type=int,
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default=1,
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help="Number of Global Memory pipelines per CU",
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)
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parser.add_argument(
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"--wfs-per-simd",
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type=int,
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default=10,
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help="Number of WF slots per SIMD",
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)
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parser.add_argument(
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"--registerManagerPolicy",
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type=str,
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default="static",
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help="Register manager policy",
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)
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parser.add_argument(
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"--vreg-file-size",
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type=int,
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default=2048,
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help="number of physical vector registers per SIMD",
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)
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parser.add_argument(
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"--vreg-min-alloc",
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type=int,
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default=4,
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help="vector register reservation unit",
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)
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parser.add_argument(
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"--sreg-file-size",
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type=int,
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default=2048,
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help="number of physical scalar registers per SIMD",
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)
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parser.add_argument(
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"--sreg-min-alloc",
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type=int,
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default=4,
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help="scalar register reservation unit",
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)
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parser.add_argument(
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"--bw-scalor",
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type=int,
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default=0,
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help="bandwidth scalor for scalability analysis",
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)
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parser.add_argument(
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"--CPUClock", type=str, default="2GHz", help="CPU clock"
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)
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parser.add_argument(
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"--gpu-clock", type=str, default="1GHz", help="GPU clock"
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)
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parser.add_argument(
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"--cpu-voltage",
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action="store",
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type=str,
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default="1.0V",
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help="CPU voltage domain",
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)
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parser.add_argument(
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"--gpu-voltage",
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action="store",
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type=str,
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default="1.0V",
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help="GPU voltage domain",
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)
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parser.add_argument(
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"--CUExecPolicy",
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type=str,
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default="OLDEST-FIRST",
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help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)",
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)
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parser.add_argument(
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"--LocalMemBarrier",
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action="store_true",
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help="Barrier does not wait for writethroughs to complete",
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)
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parser.add_argument(
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"--countPages",
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action="store_true",
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help="Count Page Accesses and output in per-CU output files",
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)
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parser.add_argument(
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"--TLB-prefetch", type=int, help="prefetch depth for TLBs"
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)
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parser.add_argument(
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"--pf-type",
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type=str,
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help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
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)
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parser.add_argument("--pf-stride", type=int, help="set prefetch stride")
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parser.add_argument(
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"--numLdsBanks",
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type=int,
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default=32,
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help="number of physical banks per LDS module",
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)
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parser.add_argument(
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"--ldsBankConflictPenalty",
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type=int,
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default=1,
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help="number of cycles per LDS bank conflict",
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)
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parser.add_argument(
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"--lds-size", type=int, default=65536, help="Size of the LDS in bytes"
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)
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parser.add_argument(
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"--num-hw-queues",
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type=int,
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default=10,
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help="number of hw queues in packet processor",
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)
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parser.add_argument(
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"--reg-alloc-policy",
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type=str,
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default="simple",
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help="register allocation policy (simple/dynamic)",
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)
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parser.add_argument(
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"--register-file-cache-size",
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type=int,
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default=0,
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help="number of registers in cache",
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)
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parser.add_argument(
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"--memtime-latency",
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type=int,
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# Set to a default of 41 from micro-benchmarks
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default=41,
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help="Latency for memtimes in scalar memory pipeline.",
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)
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