a701e1fd14
We currently use the traditional SI-like prefixes for to represent binary multipliers in some contexts. This is ambiguous in many cases since they overload the meaning of the SI prefix. Here are some examples of commonly used in the industry: * Storage vendors define 1 MB as 10**6 bytes * Memory vendors define 1 MB as 2**20 bytes * Network equipment treats 1Mbit/s as 10**6 bits/s * Memory vendors define 1Mbit as 2**20 bits In practice, this means that a FLASH chip on a storage bus uses decimal prefixes, but that same flash chip on a memory bus uses binary prefixes. It would also be reasonable to assume that the contents of a 1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet link. That's however not the case due to different meanings of the prefix. The quantity 2MX is treated differently by gem5 depending on the unit X: * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes. * Interconnect and NoC bandwidths (B/s) use binary prefixes. * Network bandwidths (bps) use decimal prefixes. * Memory sizes and storage sizes (B) use binary prefixes. Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes for binary multipliers for parameters and comments where appropriate. Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39576 Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
528 lines
24 KiB
Python
528 lines
24 KiB
Python
# Copyright (c) 2012, 2014, 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.SimObject import *
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from m5.params import *
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from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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from m5.objects.IndexingPolicies import *
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from m5.objects.ReplacementPolicies import *
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class HWPProbeEvent(object):
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def __init__(self, prefetcher, obj, *listOfNames):
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self.obj = obj
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self.prefetcher = prefetcher
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self.names = listOfNames
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def register(self):
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if self.obj:
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for name in self.names:
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self.prefetcher.getCCObject().addEventProbe(
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self.obj.getCCObject(), name)
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class BasePrefetcher(ClockedObject):
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type = 'BasePrefetcher'
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abstract = True
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cxx_class = 'Prefetcher::Base'
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cxx_header = "mem/cache/prefetch/base.hh"
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cxx_exports = [
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PyBindMethod("addEventProbe"),
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PyBindMethod("addTLB"),
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]
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sys = Param.System(Parent.any, "System this prefetcher belongs to")
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# Get the block size from the parent (system)
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block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
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on_miss = Param.Bool(False, "Only notify prefetcher on misses")
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on_read = Param.Bool(True, "Notify prefetcher on reads")
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on_write = Param.Bool(True, "Notify prefetcher on writes")
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on_data = Param.Bool(True, "Notify prefetcher on data accesses")
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on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
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prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
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"Notify the hardware prefetcher on every access (not just misses)")
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use_virtual_addresses = Param.Bool(False,
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"Use virtual addresses for prefetching")
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def __init__(self, **kwargs):
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super(BasePrefetcher, self).__init__(**kwargs)
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self._events = []
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self._tlbs = []
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def addEvent(self, newObject):
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self._events.append(newObject)
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# Override the normal SimObject::regProbeListeners method and
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# register deferred event handlers.
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def regProbeListeners(self):
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for tlb in self._tlbs:
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self.getCCObject().addTLB(tlb.getCCObject())
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for event in self._events:
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event.register()
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self.getCCObject().regProbeListeners()
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def listenFromProbe(self, simObj, *probeNames):
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if not isinstance(simObj, SimObject):
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raise TypeError("argument must be of SimObject type")
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if len(probeNames) <= 0:
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raise TypeError("probeNames must have at least one element")
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self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
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def registerTLB(self, simObj):
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if not isinstance(simObj, SimObject):
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raise TypeError("argument must be a SimObject type")
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self._tlbs.append(simObj)
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class MultiPrefetcher(BasePrefetcher):
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type = 'MultiPrefetcher'
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cxx_class = 'Prefetcher::Multi'
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cxx_header = 'mem/cache/prefetch/multi.hh'
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prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
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class QueuedPrefetcher(BasePrefetcher):
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type = "QueuedPrefetcher"
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abstract = True
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cxx_class = "Prefetcher::Queued"
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cxx_header = "mem/cache/prefetch/queued.hh"
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latency = Param.Int(1, "Latency for generated prefetches")
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queue_size = Param.Int(32, "Maximum number of queued prefetches")
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max_prefetch_requests_with_pending_translation = Param.Int(32,
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"Maximum number of queued prefetches that have a missing translation")
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queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
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queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
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cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
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tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
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# The throttle_control_percentage controls how many of the candidate
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# addresses generated by the prefetcher will be finally turned into
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# prefetch requests
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# - If set to 100, all candidates can be discarded (one request
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# will always be allowed to be generated)
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# - Setting it to 0 will disable the throttle control, so requests are
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# created for all candidates
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# - If set to 60, 40% of candidates will generate a request, and the
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# remaining 60% will be generated depending on the current accuracy
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throttle_control_percentage = Param.Percent(0, "Percentage of requests \
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that can be throttled depending on the accuracy of the prefetcher.")
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class StridePrefetcherHashedSetAssociative(SetAssociative):
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type = 'StridePrefetcherHashedSetAssociative'
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cxx_class = 'Prefetcher::StridePrefetcherHashedSetAssociative'
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cxx_header = "mem/cache/prefetch/stride.hh"
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class StridePrefetcher(QueuedPrefetcher):
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type = 'StridePrefetcher'
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cxx_class = 'Prefetcher::Stride'
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cxx_header = "mem/cache/prefetch/stride.hh"
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# Do not consult stride prefetcher on instruction accesses
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on_inst = False
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confidence_counter_bits = Param.Unsigned(3,
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"Number of bits of the confidence counter")
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initial_confidence = Param.Unsigned(4,
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"Starting confidence of new entries")
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confidence_threshold = Param.Percent(50,
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"Prefetch generation confidence threshold")
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use_requestor_id = Param.Bool(True, "Use requestor id based history")
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degree = Param.Int(4, "Number of prefetches to generate")
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table_assoc = Param.Int(4, "Associativity of the PC table")
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table_entries = Param.MemorySize("64", "Number of entries of the PC table")
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table_indexing_policy = Param.BaseIndexingPolicy(
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StridePrefetcherHashedSetAssociative(entry_size = 1,
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assoc = Parent.table_assoc, size = Parent.table_entries),
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"Indexing policy of the PC table")
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table_replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
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"Replacement policy of the PC table")
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class TaggedPrefetcher(QueuedPrefetcher):
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type = 'TaggedPrefetcher'
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cxx_class = 'Prefetcher::Tagged'
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cxx_header = "mem/cache/prefetch/tagged.hh"
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degree = Param.Int(2, "Number of prefetches to generate")
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class IndirectMemoryPrefetcher(QueuedPrefetcher):
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type = 'IndirectMemoryPrefetcher'
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cxx_class = 'Prefetcher::IndirectMemory'
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cxx_header = "mem/cache/prefetch/indirect_memory.hh"
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pt_table_entries = Param.MemorySize("16",
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"Number of entries of the Prefetch Table")
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pt_table_assoc = Param.Unsigned(16, "Associativity of the Prefetch Table")
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pt_table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.pt_table_assoc,
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size = Parent.pt_table_entries),
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"Indexing policy of the pattern table")
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pt_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the pattern table")
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max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance")
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num_indirect_counter_bits = Param.Unsigned(3,
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"Number of bits of the indirect counter")
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ipd_table_entries = Param.MemorySize("4",
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"Number of entries of the Indirect Pattern Detector")
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ipd_table_assoc = Param.Unsigned(4,
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"Associativity of the Indirect Pattern Detector")
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ipd_table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.ipd_table_assoc,
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size = Parent.ipd_table_entries),
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"Indexing policy of the Indirect Pattern Detector")
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ipd_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the Indirect Pattern Detector")
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shift_values = VectorParam.Int([2, 3, 4, -3], "Shift values to evaluate")
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addr_array_len = Param.Unsigned(4, "Number of misses tracked")
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prefetch_threshold = Param.Unsigned(2,
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"Counter threshold to start the indirect prefetching")
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stream_counter_threshold = Param.Unsigned(4,
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"Counter threshold to enable the stream prefetcher")
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streaming_distance = Param.Unsigned(4,
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"Number of prefetches to generate when using the stream prefetcher")
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class SignaturePathPrefetcher(QueuedPrefetcher):
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type = 'SignaturePathPrefetcher'
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cxx_class = 'Prefetcher::SignaturePath'
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cxx_header = "mem/cache/prefetch/signature_path.hh"
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signature_shift = Param.UInt8(3,
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"Number of bits to shift when calculating a new signature");
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signature_bits = Param.UInt16(12,
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"Size of the signature, in bits");
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signature_table_entries = Param.MemorySize("1024",
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"Number of entries of the signature table")
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signature_table_assoc = Param.Unsigned(2,
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"Associativity of the signature table")
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signature_table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.signature_table_assoc,
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size = Parent.signature_table_entries),
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"Indexing policy of the signature table")
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signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the signature table")
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num_counter_bits = Param.UInt8(3,
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"Number of bits of the saturating counters")
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pattern_table_entries = Param.MemorySize("4096",
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"Number of entries of the pattern table")
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pattern_table_assoc = Param.Unsigned(1,
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"Associativity of the pattern table")
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strides_per_pattern_entry = Param.Unsigned(4,
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"Number of strides stored in each pattern entry")
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pattern_table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.pattern_table_assoc,
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size = Parent.pattern_table_entries),
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"Indexing policy of the pattern table")
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pattern_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the pattern table")
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prefetch_confidence_threshold = Param.Float(0.5,
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"Minimum confidence to issue prefetches")
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lookahead_confidence_threshold = Param.Float(0.75,
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"Minimum confidence to continue exploring lookahead entries")
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class SignaturePathPrefetcherV2(SignaturePathPrefetcher):
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type = 'SignaturePathPrefetcherV2'
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cxx_class = 'Prefetcher::SignaturePathV2'
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cxx_header = "mem/cache/prefetch/signature_path_v2.hh"
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signature_table_entries = "256"
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signature_table_assoc = 1
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pattern_table_entries = "512"
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pattern_table_assoc = 1
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num_counter_bits = 4
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prefetch_confidence_threshold = 0.25
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lookahead_confidence_threshold = 0.25
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global_history_register_entries = Param.MemorySize("8",
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"Number of entries of global history register")
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global_history_register_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1,
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assoc = Parent.global_history_register_entries,
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size = Parent.global_history_register_entries),
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"Indexing policy of the global history register")
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global_history_register_replacement_policy = Param.BaseReplacementPolicy(
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LRURP(), "Replacement policy of the global history register")
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class AccessMapPatternMatching(ClockedObject):
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type = 'AccessMapPatternMatching'
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cxx_class = 'Prefetcher::AccessMapPatternMatching'
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cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
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block_size = Param.Unsigned(Parent.block_size,
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"Cacheline size used by the prefetcher using this object")
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limit_stride = Param.Unsigned(0,
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"Limit the strides checked up to -X/X, if 0, disable the limit")
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start_degree = Param.Unsigned(4,
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"Initial degree (Maximum number of prefetches generated")
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hot_zone_size = Param.MemorySize("2KiB", "Memory covered by a hot zone")
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access_map_table_entries = Param.MemorySize("256",
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"Number of entries in the access map table")
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access_map_table_assoc = Param.Unsigned(8,
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"Associativity of the access map table")
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access_map_table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.access_map_table_assoc,
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size = Parent.access_map_table_entries),
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"Indexing policy of the access map table")
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access_map_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the access map table")
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high_coverage_threshold = Param.Float(0.25,
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"A prefetch coverage factor bigger than this is considered high")
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low_coverage_threshold = Param.Float(0.125,
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"A prefetch coverage factor smaller than this is considered low")
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high_accuracy_threshold = Param.Float(0.5,
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"A prefetch accuracy factor bigger than this is considered high")
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low_accuracy_threshold = Param.Float(0.25,
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"A prefetch accuracy factor smaller than this is considered low")
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high_cache_hit_threshold = Param.Float(0.875,
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"A cache hit ratio bigger than this is considered high")
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low_cache_hit_threshold = Param.Float(0.75,
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"A cache hit ratio smaller than this is considered low")
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epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period")
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offchip_memory_latency = Param.Latency("30ns",
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"Memory latency used to compute the required memory bandwidth")
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class AMPMPrefetcher(QueuedPrefetcher):
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type = 'AMPMPrefetcher'
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cxx_class = 'Prefetcher::AMPM'
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cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
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ampm = Param.AccessMapPatternMatching( AccessMapPatternMatching(),
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"Access Map Pattern Matching object")
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class DeltaCorrelatingPredictionTables(SimObject):
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type = 'DeltaCorrelatingPredictionTables'
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cxx_class = 'Prefetcher::DeltaCorrelatingPredictionTables'
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cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
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deltas_per_entry = Param.Unsigned(20,
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"Number of deltas stored in each table entry")
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delta_bits = Param.Unsigned(12, "Bits per delta")
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delta_mask_bits = Param.Unsigned(8,
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"Lower bits to mask when comparing deltas")
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table_entries = Param.MemorySize("128",
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"Number of entries in the table")
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table_assoc = Param.Unsigned(128,
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"Associativity of the table")
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table_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.table_assoc,
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size = Parent.table_entries),
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"Indexing policy of the table")
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table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the table")
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class DCPTPrefetcher(QueuedPrefetcher):
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type = 'DCPTPrefetcher'
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cxx_class = 'Prefetcher::DCPT'
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cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
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dcpt = Param.DeltaCorrelatingPredictionTables(
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DeltaCorrelatingPredictionTables(),
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"Delta Correlating Prediction Tables object")
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class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
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type = "IrregularStreamBufferPrefetcher"
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cxx_class = "Prefetcher::IrregularStreamBuffer"
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cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
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num_counter_bits = Param.Unsigned(2,
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"Number of bits of the confidence counter")
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chunk_size = Param.Unsigned(256,
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"Maximum number of addresses in a temporal stream")
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degree = Param.Unsigned(4, "Number of prefetches to generate")
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training_unit_assoc = Param.Unsigned(128,
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"Associativity of the training unit")
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training_unit_entries = Param.MemorySize("128",
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"Number of entries of the training unit")
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training_unit_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc,
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size = Parent.training_unit_entries),
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"Indexing policy of the training unit")
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training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
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"Replacement policy of the training unit")
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prefetch_candidates_per_entry = Param.Unsigned(16,
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"Number of prefetch candidates stored in a SP-AMC entry")
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address_map_cache_assoc = Param.Unsigned(128,
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"Associativity of the PS/SP AMCs")
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address_map_cache_entries = Param.MemorySize("128",
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"Number of entries of the PS/SP AMCs")
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ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
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SetAssociative(entry_size = 1,
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assoc = Parent.address_map_cache_assoc,
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size = Parent.address_map_cache_entries),
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"Indexing policy of the Physical-to-Structural Address Map Cache")
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ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
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LRURP(),
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"Replacement policy of the Physical-to-Structural Address Map Cache")
|
|
sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
|
|
SetAssociative(entry_size = 1,
|
|
assoc = Parent.address_map_cache_assoc,
|
|
size = Parent.address_map_cache_entries),
|
|
"Indexing policy of the Structural-to-Physical Address Mao Cache")
|
|
sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
|
|
LRURP(),
|
|
"Replacement policy of the Structural-to-Physical Address Map Cache")
|
|
|
|
class SlimAccessMapPatternMatching(AccessMapPatternMatching):
|
|
start_degree = 2
|
|
limit_stride = 4
|
|
|
|
class SlimDeltaCorrelatingPredictionTables(DeltaCorrelatingPredictionTables):
|
|
table_entries = "256"
|
|
table_assoc = 256
|
|
deltas_per_entry = 9
|
|
|
|
class SlimAMPMPrefetcher(QueuedPrefetcher):
|
|
type = 'SlimAMPMPrefetcher'
|
|
cxx_class = 'Prefetcher::SlimAMPM'
|
|
cxx_header = "mem/cache/prefetch/slim_ampm.hh"
|
|
|
|
ampm = Param.AccessMapPatternMatching(SlimAccessMapPatternMatching(),
|
|
"Access Map Pattern Matching object")
|
|
dcpt = Param.DeltaCorrelatingPredictionTables(
|
|
SlimDeltaCorrelatingPredictionTables(),
|
|
"Delta Correlating Prediction Tables object")
|
|
|
|
class BOPPrefetcher(QueuedPrefetcher):
|
|
type = "BOPPrefetcher"
|
|
cxx_class = "Prefetcher::BOP"
|
|
cxx_header = "mem/cache/prefetch/bop.hh"
|
|
score_max = Param.Unsigned(31, "Max. score to update the best offset")
|
|
round_max = Param.Unsigned(100, "Max. round to update the best offset")
|
|
bad_score = Param.Unsigned(10, "Score at which the HWP is disabled")
|
|
rr_size = Param.Unsigned(64, "Number of entries of each RR bank")
|
|
tag_bits = Param.Unsigned(12, "Bits used to store the tag")
|
|
offset_list_size = Param.Unsigned(46,
|
|
"Number of entries in the offsets list")
|
|
negative_offsets_enable = Param.Bool(True,
|
|
"Initialize the offsets list also with negative values \
|
|
(i.e. the table will have half of the entries with positive \
|
|
offsets and the other half with negative ones)")
|
|
delay_queue_enable = Param.Bool(True, "Enable the delay queue")
|
|
delay_queue_size = Param.Unsigned(15,
|
|
"Number of entries in the delay queue")
|
|
delay_queue_cycles = Param.Cycles(60,
|
|
"Cycles to delay a write in the left RR table from the delay \
|
|
queue")
|
|
|
|
class SBOOEPrefetcher(QueuedPrefetcher):
|
|
type = 'SBOOEPrefetcher'
|
|
cxx_class = 'Prefetcher::SBOOE'
|
|
cxx_header = "mem/cache/prefetch/sbooe.hh"
|
|
latency_buffer_size = Param.Int(32, "Entries in the latency buffer")
|
|
sequential_prefetchers = Param.Int(9, "Number of sequential prefetchers")
|
|
sandbox_entries = Param.Int(1024, "Size of the address buffer")
|
|
score_threshold_pct = Param.Percent(25, "Min. threshold to issue a \
|
|
prefetch. The value is the percentage of sandbox entries to use")
|
|
|
|
class STeMSPrefetcher(QueuedPrefetcher):
|
|
type = "STeMSPrefetcher"
|
|
cxx_class = "Prefetcher::STeMS"
|
|
cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh"
|
|
|
|
spatial_region_size = Param.MemorySize("2KiB",
|
|
"Memory covered by a hot zone")
|
|
active_generation_table_entries = Param.MemorySize("64",
|
|
"Number of entries in the active generation table")
|
|
active_generation_table_assoc = Param.Unsigned(64,
|
|
"Associativity of the active generation table")
|
|
active_generation_table_indexing_policy = Param.BaseIndexingPolicy(
|
|
SetAssociative(entry_size = 1,
|
|
assoc = Parent.active_generation_table_assoc,
|
|
size = Parent.active_generation_table_entries),
|
|
"Indexing policy of the active generation table")
|
|
active_generation_table_replacement_policy = Param.BaseReplacementPolicy(
|
|
LRURP(), "Replacement policy of the active generation table")
|
|
|
|
pattern_sequence_table_entries = Param.MemorySize("16384",
|
|
"Number of entries in the pattern sequence table")
|
|
pattern_sequence_table_assoc = Param.Unsigned(16384,
|
|
"Associativity of the pattern sequence table")
|
|
pattern_sequence_table_indexing_policy = Param.BaseIndexingPolicy(
|
|
SetAssociative(entry_size = 1,
|
|
assoc = Parent.pattern_sequence_table_assoc,
|
|
size = Parent.pattern_sequence_table_entries),
|
|
"Indexing policy of the pattern sequence table")
|
|
pattern_sequence_table_replacement_policy = Param.BaseReplacementPolicy(
|
|
LRURP(), "Replacement policy of the pattern sequence table")
|
|
|
|
region_miss_order_buffer_entries = Param.Unsigned(131072,
|
|
"Number of entries of the Region Miss Order Buffer")
|
|
reconstruction_entries = Param.Unsigned(256,
|
|
"Number of reconstruction entries")
|
|
|
|
class HWPProbeEventRetiredInsts(HWPProbeEvent):
|
|
def register(self):
|
|
if self.obj:
|
|
for name in self.names:
|
|
self.prefetcher.getCCObject().addEventProbeRetiredInsts(
|
|
self.obj.getCCObject(), name)
|
|
|
|
class PIFPrefetcher(QueuedPrefetcher):
|
|
type = 'PIFPrefetcher'
|
|
cxx_class = 'Prefetcher::PIF'
|
|
cxx_header = "mem/cache/prefetch/pif.hh"
|
|
cxx_exports = [
|
|
PyBindMethod("addEventProbeRetiredInsts"),
|
|
]
|
|
|
|
prec_spatial_region_bits = Param.Unsigned(2,
|
|
"Number of preceding addresses in the spatial region")
|
|
succ_spatial_region_bits = Param.Unsigned(8,
|
|
"Number of subsequent addresses in the spatial region")
|
|
compactor_entries = Param.Unsigned(2, "Entries in the temp. compactor")
|
|
stream_address_buffer_entries = Param.Unsigned(7, "Entries in the SAB")
|
|
history_buffer_size = Param.Unsigned(16, "Entries in the history buffer")
|
|
|
|
index_entries = Param.MemorySize("64",
|
|
"Number of entries in the index")
|
|
index_assoc = Param.Unsigned(64,
|
|
"Associativity of the index")
|
|
index_indexing_policy = Param.BaseIndexingPolicy(
|
|
SetAssociative(entry_size = 1, assoc = Parent.index_assoc,
|
|
size = Parent.index_entries),
|
|
"Indexing policy of the index")
|
|
index_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
|
|
"Replacement policy of the index")
|
|
|
|
def listenFromProbeRetiredInstructions(self, simObj):
|
|
if not isinstance(simObj, SimObject):
|
|
raise TypeError("argument must be of SimObject type")
|
|
self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC"))
|