188 lines
6.8 KiB
C++
188 lines
6.8 KiB
C++
/*
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
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#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
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#include <string>
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#include <vector>
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#include "base/hashmap.hh"
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#include "base/statistics.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/CacheResourceType.hh"
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#include "mem/protocol/RubyRequest.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
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#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
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#include "mem/ruby/structures/BankedArray.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "params/RubyCache.hh"
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#include "sim/sim_object.hh"
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class CacheMemory : public SimObject
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{
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public:
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typedef RubyCacheParams Params;
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CacheMemory(const Params *p);
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~CacheMemory();
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void init();
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// Public Methods
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// perform a cache access and see if we hit or not. Return true on a hit.
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bool tryCacheAccess(Addr address, RubyRequestType type,
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DataBlock*& data_ptr);
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// similar to above, but doesn't require full access check
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bool testCacheAccess(Addr address, RubyRequestType type,
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DataBlock*& data_ptr);
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// tests to see if an address is present in the cache
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bool isTagPresent(Addr address) const;
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool cacheAvail(Addr address) const;
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// find an unused entry and sets the tag appropriate for the address
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AbstractCacheEntry* allocate(Addr address,
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AbstractCacheEntry* new_entry, bool touch);
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AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
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{
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return allocate(address, new_entry, true);
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}
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void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
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{
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allocate(address, new_entry, true);
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}
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// Explicitly free up this address
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void deallocate(Addr address);
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// Returns with the physical address of the conflicting cache line
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Addr cacheProbe(Addr address) const;
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// looks an address up in the cache
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AbstractCacheEntry* lookup(Addr address);
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const AbstractCacheEntry* lookup(Addr address) const;
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Cycles getTagLatency() const { return tagArray.getLatency(); }
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Cycles getDataLatency() const { return dataArray.getLatency(); }
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bool isBlockInvalid(int64_t cache_set, int64_t loc);
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bool isBlockNotBusy(int64_t cache_set, int64_t loc);
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// Hook for checkpointing the contents of the cache
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void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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// Set this address to most recently used
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void setMRU(Addr address);
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// Functions for locking and unlocking cache lines corresponding to the
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// provided address. These are required for supporting atomic memory
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// accesses. These are to be used when only the address of the cache entry
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// is available. In case the entry itself is available. use the functions
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// provided by the AbstractCacheEntry class.
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void setLocked (Addr addr, int context);
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void clearLocked (Addr addr);
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bool isLocked (Addr addr, int context);
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// Print cache contents
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void print(std::ostream& out) const;
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void printData(std::ostream& out) const;
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void regStats();
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bool checkResourceAvailable(CacheResourceType res, Addr addr);
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void recordRequestType(CacheRequestType requestType, Addr addr);
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public:
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Stats::Scalar m_demand_hits;
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Stats::Scalar m_demand_misses;
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Stats::Formula m_demand_accesses;
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Stats::Scalar m_sw_prefetches;
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Stats::Scalar m_hw_prefetches;
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Stats::Formula m_prefetches;
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Stats::Vector m_accessModeType;
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Stats::Scalar numDataArrayReads;
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Stats::Scalar numDataArrayWrites;
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Stats::Scalar numTagArrayReads;
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Stats::Scalar numTagArrayWrites;
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Stats::Scalar numTagArrayStalls;
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Stats::Scalar numDataArrayStalls;
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int getCacheSize() const { return m_cache_size; }
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int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
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Addr getAddressAtIdx(int idx) const;
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private:
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// convert a Address to its location in the cache
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int64_t addressToCacheSet(Addr address) const;
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// Given a cache tag: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int findTagInSet(int64_t line, Addr tag) const;
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int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
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// Private copy constructor and assignment operator
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CacheMemory(const CacheMemory& obj);
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CacheMemory& operator=(const CacheMemory& obj);
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private:
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// Data Members (m_prefix)
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bool m_is_instruction_only_cache;
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// The first index is the # of cache lines.
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// The second index is the the amount associativity.
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m5::hash_map<Addr, int> m_tag_index;
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std::vector<std::vector<AbstractCacheEntry*> > m_cache;
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AbstractReplacementPolicy *m_replacementPolicy_ptr;
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BankedArray dataArray;
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BankedArray tagArray;
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int m_cache_size;
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int m_cache_num_sets;
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int m_cache_num_set_bits;
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int m_cache_assoc;
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int m_start_index_bit;
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bool m_resource_stalls;
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};
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std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
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#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
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