a5f55e0be1
New topology ripped from Fiji to support dGPU. A dGPU flag is added to the config which is propogated to the driver. The emulated driver is now able to properly deal with dGPU ioctls and mmaps. For now, dGPU physical memory is allocated from the host, but this is easy to change once we get a GPU memory controller up and running. Change-Id: I594418482b12ec8fb2e4018d8d0371d56f4f51c8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42214 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
638 lines
26 KiB
C++
638 lines
26 KiB
C++
/*
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* Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gpu-compute/gpu_compute_driver.hh"
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#include "cpu/thread_context.hh"
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#include "debug/GPUDriver.hh"
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#include "dev/hsa/hsa_device.hh"
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#include "dev/hsa/hsa_packet_processor.hh"
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#include "dev/hsa/kfd_event_defines.h"
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#include "dev/hsa/kfd_ioctl.h"
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#include "params/GPUComputeDriver.hh"
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#include "sim/process.hh"
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#include "sim/syscall_emul_buf.hh"
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GPUComputeDriver::GPUComputeDriver(const Params &p)
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: HSADriver(p), isdGPU(p.isdGPU)
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{
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device->attachDriver(this);
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DPRINTF(GPUDriver, "Constructing KFD: device\n");
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}
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int
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GPUComputeDriver::ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf)
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{
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auto &virt_proxy = tc->getVirtProxy();
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switch (req) {
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case AMDKFD_IOC_GET_VERSION:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_GET_VERSION\n");
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TypedBufferArg<kfd_ioctl_get_version_args> args(ioc_buf);
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args->major_version = KFD_IOCTL_MAJOR_VERSION;
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args->minor_version = KFD_IOCTL_MINOR_VERSION;
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args.copyOut(virt_proxy);
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}
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break;
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case AMDKFD_IOC_CREATE_QUEUE:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_CREATE_QUEUE\n");
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allocateQueue(tc, ioc_buf);
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DPRINTF(GPUDriver, "Creating queue %d\n", queueId);
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}
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break;
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case AMDKFD_IOC_DESTROY_QUEUE:
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{
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TypedBufferArg<kfd_ioctl_destroy_queue_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_DESTROY_QUEUE;" \
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"queue offset %d\n", args->queue_id);
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device->hsaPacketProc().unsetDeviceQueueDesc(args->queue_id);
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}
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break;
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case AMDKFD_IOC_SET_MEMORY_POLICY:
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{
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/**
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* This is where the runtime requests MTYPE from an aperture.
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* Basically, the globally memory aperture is divided up into
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* a default aperture and an alternate aperture each of which have
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* their own MTYPE policies. This is done to mark a small piece
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* of the global memory as uncacheable. Host memory mappings will
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* be carved out of this uncacheable aperture, which is how they
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* implement 'coherent' host/device memory on dGPUs.
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*
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* TODO: Need to reflect per-aperture MTYPE policies based on this
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* call.
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*
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*/
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warn("unimplemented ioctl: AMDKFD_IOC_SET_MEMORY_POLICY\n");
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}
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break;
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case AMDKFD_IOC_GET_CLOCK_COUNTERS:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_GET_CLOCK_COUNTERS\n");
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TypedBufferArg<kfd_ioctl_get_clock_counters_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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// Set nanosecond resolution
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args->system_clock_freq = 1000000000;
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/**
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* Derive all clock counters based on the tick. All
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* device clocks are identical and perfectly in sync.
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*/
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uint64_t elapsed_nsec = curTick() / SimClock::Int::ns;
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args->gpu_clock_counter = elapsed_nsec;
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args->cpu_clock_counter = elapsed_nsec;
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args->system_clock_counter = elapsed_nsec;
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args.copyOut(virt_proxy);
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}
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break;
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case AMDKFD_IOC_GET_PROCESS_APERTURES:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_GET_PROCESS_APERTURES\n");
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TypedBufferArg<kfd_ioctl_get_process_apertures_args> args(ioc_buf);
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args->num_of_nodes = 1;
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/**
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* Set the GPUVM/LDS/Scratch APEs exactly as they
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* are in the real driver, see the KFD driver
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* in the ROCm Linux kernel source:
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* drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
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*/
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for (int i = 0; i < args->num_of_nodes; ++i) {
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/**
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* While the GPU node numbers start at 0, we add 1
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* to force the count to start at 1. This is to
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* ensure that the base/limit addresses are
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* calculated correctly.
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*/
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args->process_apertures[i].scratch_base
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= scratchApeBase(i + 1);
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args->process_apertures[i].scratch_limit =
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scratchApeLimit(args->process_apertures[i].scratch_base);
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args->process_apertures[i].lds_base = ldsApeBase(i + 1);
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args->process_apertures[i].lds_limit =
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ldsApeLimit(args->process_apertures[i].lds_base);
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args->process_apertures[i].gpuvm_base = gpuVmApeBase(i + 1);
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args->process_apertures[i].gpuvm_limit =
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gpuVmApeLimit(args->process_apertures[i].gpuvm_base);
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// NOTE: Must match ID populated by hsaTopology.py
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if (isdGPU)
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args->process_apertures[i].gpu_id = 50156;
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else
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args->process_apertures[i].gpu_id = 2765;
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DPRINTF(GPUDriver, "GPUVM base for node[%i] = %#x\n", i,
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args->process_apertures[i].gpuvm_base);
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DPRINTF(GPUDriver, "GPUVM limit for node[%i] = %#x\n", i,
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args->process_apertures[i].gpuvm_limit);
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DPRINTF(GPUDriver, "LDS base for node[%i] = %#x\n", i,
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args->process_apertures[i].lds_base);
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DPRINTF(GPUDriver, "LDS limit for node[%i] = %#x\n", i,
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args->process_apertures[i].lds_limit);
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DPRINTF(GPUDriver, "Scratch base for node[%i] = %#x\n", i,
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args->process_apertures[i].scratch_base);
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DPRINTF(GPUDriver, "Scratch limit for node[%i] = %#x\n", i,
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args->process_apertures[i].scratch_limit);
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/**
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* The CPU's 64b address space can only use the
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* areas with VA[63:47] == 0x1ffff or VA[63:47] == 0,
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* therefore we must ensure that the apertures do not
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* fall in the CPU's address space.
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*/
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assert(bits<Addr>(args->process_apertures[i].scratch_base, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].scratch_base, 63,
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47) != 0);
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assert(bits<Addr>(args->process_apertures[i].scratch_limit, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].scratch_limit, 63,
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47) != 0);
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assert(bits<Addr>(args->process_apertures[i].lds_base, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].lds_base, 63,
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47) != 0);
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assert(bits<Addr>(args->process_apertures[i].lds_limit, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].lds_limit, 63,
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47) != 0);
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assert(bits<Addr>(args->process_apertures[i].gpuvm_base, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].gpuvm_base, 63,
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47) != 0);
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assert(bits<Addr>(args->process_apertures[i].gpuvm_limit, 63,
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47) != 0x1ffff);
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assert(bits<Addr>(args->process_apertures[i].gpuvm_limit, 63,
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47) != 0);
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}
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args.copyOut(virt_proxy);
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}
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break;
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case AMDKFD_IOC_UPDATE_QUEUE:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_UPDATE_QUEUE\n");
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}
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break;
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case AMDKFD_IOC_CREATE_EVENT:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_CREATE_EVENT\n");
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TypedBufferArg<kfd_ioctl_create_event_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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if (args->event_type != KFD_IOC_EVENT_SIGNAL) {
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fatal("Signal events are only supported currently\n");
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} else if (eventSlotIndex == SLOTS_PER_PAGE) {
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fatal("Signal event wasn't created; signal limit reached\n");
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}
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// Currently, we allocate only one signal_page for events.
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// Note that this signal page is of size 8 * KFD_SIGNAL_EVENT_LIMIT
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uint64_t page_index = 0;
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args->event_page_offset = (page_index | KFD_MMAP_TYPE_EVENTS);
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args->event_page_offset <<= PAGE_SHIFT;
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// TODO: Currently we support only signal events, hence using
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// the same ID for both signal slot and event slot
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args->event_slot_index = eventSlotIndex;
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args->event_id = eventSlotIndex++;
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args->event_trigger_data = args->event_id;
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DPRINTF(GPUDriver, "amdkfd create events"
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"(event_id: 0x%x, offset: 0x%x)\n",
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args->event_id, args->event_page_offset);
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// Since eventSlotIndex is increased everytime a new event is
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// created ETable at eventSlotIndex(event_id) is guaranteed to be
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// empty. In a future implementation that reuses deleted event_ids,
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// we should check if event table at this
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// eventSlotIndex(event_id) is empty before inserting a new event
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// table entry
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ETable.emplace(std::pair<uint32_t, ETEntry>(args->event_id, {}));
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args.copyOut(virt_proxy);
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}
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break;
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case AMDKFD_IOC_DESTROY_EVENT:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_DESTROY_EVENT\n");
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TypedBufferArg<kfd_ioctl_destroy_event_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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DPRINTF(GPUDriver, "amdkfd destroying event %d\n", args->event_id);
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fatal_if(ETable.count(args->event_id) == 0,
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"Event ID invalid, cannot destroy this event\n");
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ETable.erase(args->event_id);
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}
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break;
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case AMDKFD_IOC_SET_EVENT:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_SET_EVENTS\n");
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TypedBufferArg<kfd_ioctl_set_event_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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DPRINTF(GPUDriver, "amdkfd set event %d\n", args->event_id);
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fatal_if(ETable.count(args->event_id) == 0,
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"Event ID invlaid, cannot set this event\n");
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ETable[args->event_id].setEvent = true;
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signalWakeupEvent(args->event_id);
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}
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break;
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case AMDKFD_IOC_RESET_EVENT:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_RESET_EVENT\n");
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}
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break;
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case AMDKFD_IOC_WAIT_EVENTS:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_WAIT_EVENTS\n");
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TypedBufferArg<kfd_ioctl_wait_events_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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kfd_event_data *events =
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(kfd_event_data *)args->events_ptr;
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DPRINTF(GPUDriver, "amdkfd wait for events"
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"(wait on all: %d, timeout : %d, num_events: %s)\n",
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args->wait_for_all, args->timeout, args->num_events);
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panic_if(args->wait_for_all != 0 && args->num_events > 1,
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"Wait for all events not supported\n");
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bool should_sleep = true;
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if (TCEvents.count(tc) == 0) {
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// This thread context trying to wait on an event for the first
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// time, initialize it.
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TCEvents.emplace(std::piecewise_construct, std::make_tuple(tc),
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std::make_tuple(this, tc));
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DPRINTF(GPUDriver, "\tamdkfd creating event list"
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" for thread %d\n", tc->cpuId());
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}
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panic_if(TCEvents[tc].signalEvents.size() != 0,
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"There are %d events that put this thread to sleep,"
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" this thread should not be running\n",
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TCEvents[tc].signalEvents.size());
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for (int i = 0; i < args->num_events; i++) {
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panic_if(!events,
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"Event pointer invalid\n");
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Addr eventDataAddr = (Addr)(events + i);
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TypedBufferArg<kfd_event_data> EventData(
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eventDataAddr, sizeof(kfd_event_data));
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EventData.copyIn(virt_proxy);
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DPRINTF(GPUDriver,
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"\tamdkfd wait for event %d\n", EventData->event_id);
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panic_if(ETable.count(EventData->event_id) == 0,
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"Event ID invalid, cannot set this event\n");
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panic_if(ETable[EventData->event_id].threadWaiting,
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"Multiple threads waiting on the same event\n");
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if (ETable[EventData->event_id].setEvent) {
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// If event is already set, the event has already happened.
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// Just unset the event and dont put this thread to sleep.
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ETable[EventData->event_id].setEvent = false;
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should_sleep = false;
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}
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if (should_sleep) {
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// Put this thread to sleep
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ETable[EventData->event_id].threadWaiting = true;
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ETable[EventData->event_id].tc = tc;
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TCEvents[tc].signalEvents.insert(EventData->event_id);
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}
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}
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// TODO: Return the correct wait_result back. Currently, returning
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// success for both KFD_WAIT_TIMEOUT and KFD_WAIT_COMPLETE.
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// Ideally, this needs to be done after the event is triggered and
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// after the thread is woken up.
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args->wait_result = 0;
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args.copyOut(virt_proxy);
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if (should_sleep) {
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// Put this thread to sleep
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sleepCPU(tc, args->timeout);
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} else {
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// Remove events that tried to put this thread to sleep
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TCEvents[tc].clearEvents();
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}
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}
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break;
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case AMDKFD_IOC_DBG_REGISTER:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_DBG_REGISTER\n");
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}
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break;
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case AMDKFD_IOC_DBG_UNREGISTER:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_DBG_UNREGISTER\n");
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}
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break;
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case AMDKFD_IOC_DBG_ADDRESS_WATCH:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_DBG_ADDRESS_WATCH\n");
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}
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break;
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case AMDKFD_IOC_DBG_WAVE_CONTROL:
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{
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warn("unimplemented ioctl: AMDKFD_IOC_DBG_WAVE_CONTROL\n");
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}
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break;
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/**
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* In real hardware, this IOCTL maps host memory, dGPU memory, or dGPU
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* doorbells into GPUVM space. Essentially, ROCm implements SVM by
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* carving out a region of free VA space that both the host and GPUVM
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* can agree upon. The entire GPU VA space is reserved on the host
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* using a fixed mmap at a low VA range that is also directly
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* accessable by the GPU's limited number of VA bits. When we actually
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* call memory allocation later in the program, this IOCTL is invoked
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* to create BOs/VMAs in the driver and bind them to physical
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* memory/doorbells.
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*
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* For gem5, we don't need to carve out any GPUVM space here (we don't
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* support GPUVM and use host page tables on the GPU directly). We can
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* can just use the existing host SVM region. We comment on each memory
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* type seperately.
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*/
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case AMDKFD_IOC_ALLOC_MEMORY_OF_GPU:
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{
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DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_ALLOC_MEMORY_OF_GPU\n");
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TypedBufferArg<kfd_ioctl_alloc_memory_of_gpu_args> args(ioc_buf);
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args.copyIn(virt_proxy);
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assert(isdGPU);
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assert((args->va_addr % TheISA::PageBytes) == 0);
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Addr mmap_offset = 0;
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if (KFD_IOC_ALLOC_MEM_FLAGS_VRAM & args->flags) {
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DPRINTF(GPUDriver, "amdkfd allocation type: VRAM\n");
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args->mmap_offset = args->va_addr;
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// VRAM allocations are device memory mapped into GPUVM
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// space.
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//
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// We can't rely on the lazy host allocator (fixupFault) to
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// handle this mapping since it needs to be placed in dGPU
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// framebuffer memory. The lazy allocator will try to place
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// this in host memory.
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//
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// TODO: We don't have the appropriate bifurcation of the
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// physical address space with different memory controllers
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// yet. This is where we will explicitly add the PT maps to
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// dGPU memory in the future.
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} else if (KFD_IOC_ALLOC_MEM_FLAGS_USERPTR & args->flags) {
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DPRINTF(GPUDriver, "amdkfd allocation type: USERPTR\n");
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mmap_offset = args->mmap_offset;
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// USERPTR allocations are system memory mapped into GPUVM
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// space. The user provides the driver with the pointer.
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//
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// No action needs to be taken for this memory type. We will
|
|
// lazily map it into host memory on first touch.
|
|
} else if (KFD_IOC_ALLOC_MEM_FLAGS_GTT & args->flags) {
|
|
DPRINTF(GPUDriver, "amdkfd allocation type: GTT\n");
|
|
args->mmap_offset = args->va_addr;
|
|
// GTT allocations are system memory mapped into GPUVM space.
|
|
// It's different than a USERPTR allocation since the driver
|
|
// itself allocates the physical memory on the host.
|
|
//
|
|
// No action needs to be taken for this memory type. We will
|
|
// lazily map it into host memory on first touch. The
|
|
// fixupFault will find the original SVM aperture mapped to the
|
|
// host.
|
|
//
|
|
// Note that for GTT the thunk layer needs to call mmap on the
|
|
// driver FD later if it wants the host to have access to this
|
|
// memory (which it probably does).
|
|
} else if (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL & args->flags) {
|
|
DPRINTF(GPUDriver, "amdkfd allocation type: DOORBELL\n");
|
|
// DOORBELL allocations are the queue doorbells that are
|
|
// memory mapped into GPUVM space.
|
|
//
|
|
// Explicitly map this virtual address to our PIO doorbell
|
|
// interface in the page tables (non-cacheable)
|
|
tc->getProcessPtr()->pTable->map(args->va_addr,
|
|
device->hsaPacketProc().pioAddr,
|
|
args->size, false);
|
|
break;
|
|
}
|
|
|
|
DPRINTF(GPUDriver, "amdkfd allocation arguments: va_addr %p "
|
|
"size %lu, mmap_offset %p, gpu_id %d\n",
|
|
args->va_addr, args->size, mmap_offset, args->gpu_id);
|
|
|
|
// TODO: Not sure where the handle is used yet. Set it to an
|
|
// easily trackable value.
|
|
args->handle= 0xdeadbeef;
|
|
args.copyOut(virt_proxy);
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_FREE_MEMORY_OF_GPU:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_FREE_MEMORY_OF_GPU\n");
|
|
}
|
|
break;
|
|
/**
|
|
* Called to map an already allocated region of memory to this GPU's
|
|
* GPUVM VA space. We don't need to implement this in the simulator
|
|
* since we only have a single VM system. If the region has already
|
|
* been allocated somewhere like the CPU, then it's already visible
|
|
* to the device.
|
|
*/
|
|
case AMDKFD_IOC_MAP_MEMORY_TO_GPU:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_MAP_MEMORY_TO_GPU\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_ALLOC_MEMORY_OF_SCRATCH\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_SET_CU_MASK:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_SET_CU_MASK\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_SET_PROCESS_DGPU_APERTURE:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_SET_PROCESS_DGPU_APERTURE"
|
|
"\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_SET_TRAP_HANDLER:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_SET_TRAP_HANDLER\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_GET_PROCESS_APERTURES_NEW:
|
|
{
|
|
DPRINTF(GPUDriver,
|
|
"ioctl: AMDKFD_IOC_GET_PROCESS_APERTURES_NEW\n");
|
|
|
|
TypedBufferArg<kfd_ioctl_get_process_apertures_new_args>
|
|
ioc_args(ioc_buf);
|
|
|
|
ioc_args.copyIn(virt_proxy);
|
|
ioc_args->num_of_nodes = 1;
|
|
|
|
for (int i = 0; i < ioc_args->num_of_nodes; ++i) {
|
|
TypedBufferArg<kfd_process_device_apertures> ape_args
|
|
(ioc_args->kfd_process_device_apertures_ptr);
|
|
|
|
ape_args->scratch_base = scratchApeBase(i + 1);
|
|
ape_args->scratch_limit =
|
|
scratchApeLimit(ape_args->scratch_base);
|
|
ape_args->lds_base = ldsApeBase(i + 1);
|
|
ape_args->lds_limit = ldsApeLimit(ape_args->lds_base);
|
|
ape_args->gpuvm_base = gpuVmApeBase(i + 1);
|
|
ape_args->gpuvm_limit = gpuVmApeLimit(ape_args->gpuvm_base);
|
|
|
|
// NOTE: Must match ID populated by hsaTopology.py
|
|
if (isdGPU)
|
|
ape_args->gpu_id = 50156;
|
|
else
|
|
ape_args->gpu_id = 2765;
|
|
|
|
assert(bits<Addr>(ape_args->scratch_base, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->scratch_base, 63, 47) != 0);
|
|
assert(bits<Addr>(ape_args->scratch_limit, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->scratch_limit, 63, 47) != 0);
|
|
assert(bits<Addr>(ape_args->lds_base, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->lds_base, 63, 47) != 0);
|
|
assert(bits<Addr>(ape_args->lds_limit, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->lds_limit, 63, 47) != 0);
|
|
assert(bits<Addr>(ape_args->gpuvm_base, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->gpuvm_base, 63, 47) != 0);
|
|
assert(bits<Addr>(ape_args->gpuvm_limit, 63, 47) != 0x1ffff);
|
|
assert(bits<Addr>(ape_args->gpuvm_limit, 63, 47) != 0);
|
|
|
|
ape_args.copyOut(virt_proxy);
|
|
}
|
|
|
|
ioc_args.copyOut(virt_proxy);
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_GET_DMABUF_INFO:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_GET_DMABUF_INFO\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_IMPORT_DMABUF:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_IMPORT_DMABUF\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_GET_TILE_CONFIG:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_GET_TILE_CONFIG\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_IPC_IMPORT_HANDLE:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_IPC_IMPORT_HANDLE\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_IPC_EXPORT_HANDLE:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_IPC_EXPORT_HANDLE\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_CROSS_MEMORY_COPY:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_CROSS_MEMORY_COPY\n");
|
|
}
|
|
break;
|
|
case AMDKFD_IOC_OPEN_GRAPHIC_HANDLE:
|
|
{
|
|
warn("unimplemented ioctl: AMDKFD_IOC_OPEN_GRAPHIC_HANDLE\n");
|
|
}
|
|
break;
|
|
default:
|
|
fatal("%s: bad ioctl %d\n", req);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
GPUComputeDriver::sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout)
|
|
{
|
|
// Convert millisecs to ticks
|
|
Tick wakeup_delay((uint64_t)milliSecTimeout * 1000000000);
|
|
assert(TCEvents.count(tc) == 1);
|
|
TCEvents[tc].timerEvent.scheduleWakeup(wakeup_delay);
|
|
tc->suspend();
|
|
DPRINTF(GPUDriver,
|
|
"CPU %d is put to sleep\n", tc->cpuId());
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::gpuVmApeBase(int gpuNum) const
|
|
{
|
|
return ((Addr)gpuNum << 61) + 0x1000000000000L;
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::gpuVmApeLimit(Addr apeBase) const
|
|
{
|
|
return (apeBase & 0xFFFFFF0000000000UL) | 0xFFFFFFFFFFL;
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::scratchApeBase(int gpuNum) const
|
|
{
|
|
return ((Addr)gpuNum << 61) + 0x100000000L;
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::scratchApeLimit(Addr apeBase) const
|
|
{
|
|
return (apeBase & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF;
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::ldsApeBase(int gpuNum) const
|
|
{
|
|
return ((Addr)gpuNum << 61) + 0x0;
|
|
}
|
|
|
|
Addr
|
|
GPUComputeDriver::ldsApeLimit(Addr apeBase) const
|
|
{
|
|
return (apeBase & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF;
|
|
}
|