Andreas Hansson 806a1144ce scons: Use c++0x with gcc >= 4.4 instead of 4.6 ...

This patch shifts the version of gcc for which we enable c++0x from
4.6 to 4.4 The more long term plan is to see what the c++0x features
can bring and what level of support would be enabled simply by bumping
the required version of gcc from 4.3 to 4.4.

A few minor things had to be fixed in the code base, most notably the
choice of a hashmap implementation. In the Ruby Sequencer there were
also a few minor issues that gcc 4.4 was not too happy about.

2012-09-14 12:13:18 -04:00

..

cache

clang: Fix issues identified by the clang static analyzer

2012-09-11 14:15:47 -04:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

Ruby: Modify Scons so that we can put .sm files in extras

2012-09-12 14:52:04 -05:00

ruby

scons: Use c++0x with gcc >= 4.4 instead of 4.6

2012-09-14 12:13:18 -04:00

slicc

Ruby: Modify Scons so that we can put .sm files in extras

2012-09-12 14:52:04 -05:00

abstract_mem.cc

Mem: Allow serializing of more than INT_MAX bytes

2012-09-10 11:57:43 -04:00

abstract_mem.hh

Mem: Make members relating to range and size constant

2012-07-09 12:35:44 -04:00

AbstractMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

bridge.cc

Clock: Add a Cycles wrapper class and use where applicable

2012-08-28 14:30:33 -04:00

bridge.hh

Clock: Add a Cycles wrapper class and use where applicable

2012-08-28 14:30:33 -04:00

Bridge.py

Bridge: Remove NACKs in the bridge and unify with packet queue

2012-08-22 11:39:58 -04:00

bus.cc

Clock: Move the clock and related functions to ClockedObject

2012-08-21 05:49:01 -04:00

bus.hh

Clock: Move the clock and related functions to ClockedObject

2012-08-21 05:49:01 -04:00

Bus.py

Param: Transition to Cycles for relevant parameters

2012-09-07 12:34:38 -04:00

coherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

coherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

comm_monitor.cc

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

comm_monitor.hh

Port: Make getAddrRanges const

2012-07-09 12:35:34 -04:00

CommMonitor.py

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

fs_translating_port_proxy.cc

mem: fix bug with CopyStringOut and null string termination.

2012-05-10 18:04:27 -05:00

fs_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.cc

Clock: Move the clock and related functions to ClockedObject

2012-08-21 05:49:01 -04:00

mem_object.hh

Clock: Move the clock and related functions to ClockedObject

2012-08-21 05:49:01 -04:00

MemObject.py

Clock: Move the clock and related functions to ClockedObject

2012-08-21 05:49:01 -04:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

Port: Align port names in C++ and Python

2012-07-09 12:35:39 -04:00

noncoherent_bus.hh

Bus: Split the bus into separate request/response layers

2012-07-09 12:35:37 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

Port: Extend the QueuedPort interface and use where appropriate

2012-08-22 11:39:56 -04:00

packet_queue.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet.cc

Packet: Remove NACKs from packet and its use in endpoints

2012-08-22 11:39:59 -04:00

packet.hh

Packet: Remove NACKs from packet and its use in endpoints

2012-08-22 11:39:59 -04:00

page_table.cc

Fix: Address a few benign memory leaks

2012-07-09 12:35:30 -04:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

physical.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

port_proxy.cc

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

port.cc

Port: Stricter port bind/unbind semantics

2012-08-28 14:30:27 -04:00

port.hh

Port: Stricter port bind/unbind semantics

2012-08-28 14:30:27 -04:00

qport.hh

Port: Extend the QueuedPort interface and use where appropriate

2012-08-22 11:39:56 -04:00

request.hh

sim: Remove FastAlloc

2012-06-05 01:23:08 -04:00

SConscript

Bridge: Remove NACKs in the bridge and unify with packet queue

2012-08-22 11:39:58 -04:00

se_translating_port_proxy.cc

SETranslatingPortProxy: fix bug in tryReadString()

2012-08-06 16:57:11 -07:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_mem.cc

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

simple_mem.hh

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

SimpleMemory.py

Mem: Make SimpleMemory single ported

2012-07-12 12:56:13 -04:00

tport.cc

Port: Extend the QueuedPort interface and use where appropriate

2012-08-22 11:39:56 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00