a575fbd4aa
and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. --HG-- extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb
121 lines
4.5 KiB
Python
121 lines
4.5 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2004-2005 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Nathan Binkert
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import os
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Import('*')
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Source('swig/init.cc')
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Source('swig/pyevent.cc')
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Source('swig/pyobject.cc')
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PySource('m5', 'm5/__init__.py')
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PySource('m5', 'm5/SimObject.py')
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PySource('m5', 'm5/attrdict.py')
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PySource('m5', 'm5/convert.py')
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PySource('m5', 'm5/event.py')
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PySource('m5', 'm5/main.py')
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PySource('m5', 'm5/multidict.py')
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PySource('m5', 'm5/params.py')
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PySource('m5', 'm5/proxy.py')
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PySource('m5', 'm5/smartdict.py')
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PySource('m5', 'm5/stats.py')
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PySource('m5', 'm5/ticks.py')
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PySource('m5', 'm5/util.py')
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PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py'))
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SwigSource('m5.internal', 'swig/core.i')
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SwigSource('m5.internal', 'swig/debug.i')
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SwigSource('m5.internal', 'swig/event.i')
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SwigSource('m5.internal', 'swig/random.i')
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SwigSource('m5.internal', 'swig/sim_object.i')
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SwigSource('m5.internal', 'swig/stats.i')
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SwigSource('m5.internal', 'swig/trace.i')
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PySource('m5.internal', 'm5/internal/__init__.py')
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SimObject('m5/objects/AlphaConsole.py')
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SimObject('m5/objects/AlphaTLB.py')
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SimObject('m5/objects/BadDevice.py')
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SimObject('m5/objects/BaseCPU.py')
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SimObject('m5/objects/BaseCache.py')
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SimObject('m5/objects/BaseHier.py')
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SimObject('m5/objects/BaseMem.py')
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SimObject('m5/objects/BaseMemory.py')
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SimObject('m5/objects/BranchPred.py')
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SimObject('m5/objects/Bridge.py')
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SimObject('m5/objects/Bus.py')
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SimObject('m5/objects/Checker.py')
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SimObject('m5/objects/CoherenceProtocol.py')
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SimObject('m5/objects/DRAMMemory.py')
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SimObject('m5/objects/Device.py')
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SimObject('m5/objects/DiskImage.py')
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SimObject('m5/objects/Ethernet.py')
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SimObject('m5/objects/FUPool.py')
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SimObject('m5/objects/FastCPU.py')
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#SimObject('m5/objects/FreebsdSystem.py')
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SimObject('m5/objects/FullCPU.py')
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SimObject('m5/objects/FuncUnit.py')
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SimObject('m5/objects/FuncUnitConfig.py')
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SimObject('m5/objects/FunctionalMemory.py')
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SimObject('m5/objects/HierParams.py')
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SimObject('m5/objects/Ide.py')
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SimObject('m5/objects/IntrControl.py')
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SimObject('m5/objects/LinuxSystem.py')
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SimObject('m5/objects/MainMemory.py')
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SimObject('m5/objects/MemObject.py')
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SimObject('m5/objects/MemTest.py')
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SimObject('m5/objects/MemoryController.py')
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SimObject('m5/objects/O3CPU.py')
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SimObject('m5/objects/OzoneCPU.py')
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SimObject('m5/objects/Pci.py')
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SimObject('m5/objects/PhysicalMemory.py')
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SimObject('m5/objects/PipeTrace.py')
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SimObject('m5/objects/Platform.py')
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SimObject('m5/objects/Process.py')
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SimObject('m5/objects/Repl.py')
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SimObject('m5/objects/Root.py')
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SimObject('m5/objects/Sampler.py')
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SimObject('m5/objects/Scsi.py')
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SimObject('m5/objects/SimConsole.py')
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SimObject('m5/objects/SimpleCPU.py')
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SimObject('m5/objects/SimpleDisk.py')
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#SimObject('m5/objects/SimpleOzoneCPU.py')
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SimObject('m5/objects/SparcTLB.py')
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SimObject('m5/objects/System.py')
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SimObject('m5/objects/T1000.py')
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#SimObject('m5/objects/Tru64System.py')
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SimObject('m5/objects/Tsunami.py')
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SimObject('m5/objects/Uart.py')
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if env['ALPHA_TLASER']:
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SimObject('m5/objects/DmaEngine.py')
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SimObject('m5/objects/Turbolaser.py')
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