7daeed83f7
The proxies this method initializes no longer exist, since they're now created locally. Change-Id: I5fd1c99fbc00f5057ea8868e91be02d577b1c176 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45909 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
569 lines
18 KiB
C++
569 lines
18 KiB
C++
/*
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* Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_THREAD_HH__
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#define __CPU_SIMPLE_THREAD_HH__
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#include <algorithm>
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#include <vector>
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#include "arch/decoder.hh"
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#include "arch/generic/htm.hh"
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#include "arch/generic/mmu.hh"
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#include "arch/generic/tlb.hh"
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#include "arch/isa.hh"
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#include "arch/pcstate.hh"
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#include "arch/vecregs.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "debug/CCRegs.hh"
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#include "debug/FloatRegs.hh"
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#include "debug/IntRegs.hh"
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#include "debug/VecPredRegs.hh"
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#include "debug/VecRegs.hh"
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#include "mem/htm.hh"
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#include "mem/page_table.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/serialize.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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class BaseCPU;
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class CheckerCPU;
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/**
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* The SimpleThread object provides a combination of the ThreadState
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* object and the ThreadContext interface. It implements the
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* ThreadContext interface and adds to the ThreadState object by adding all
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* the objects needed for simple functional execution, including a
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* simple architectural register file, and pointers to the ITB and DTB
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* in full system mode. For CPU models that do not need more advanced
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* ways to hold state (i.e. a separate physical register file, or
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* separate fetch and commit PC's), this SimpleThread class provides
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* all the necessary state for full architecture-level functional
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* simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
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* examples.
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*/
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class SimpleThread : public ThreadState, public ThreadContext
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{
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public:
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typedef ThreadContext::Status Status;
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protected:
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std::vector<RegVal> floatRegs;
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std::vector<RegVal> intRegs;
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std::vector<TheISA::VecRegContainer> vecRegs;
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std::vector<TheISA::VecPredRegContainer> vecPredRegs;
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std::vector<RegVal> ccRegs;
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TheISA::ISA *const isa; // one "instance" of the current ISA.
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TheISA::PCState _pcState;
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// hardware transactional memory
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std::unique_ptr<BaseHTMCheckpoint> _htmCheckpoint;
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/** Did this instruction execute or is it predicated false */
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bool predicate;
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/** True if the memory access should be skipped for this instruction */
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bool memAccPredicate;
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public:
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std::string
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name() const
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{
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return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
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}
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PCEventQueue pcEventQueue;
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/**
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* An instruction-based event queue. Used for scheduling events based on
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* number of instructions committed.
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*/
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EventQueue comInstEventQueue;
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System *system;
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BaseMMU *mmu;
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TheISA::Decoder decoder;
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// hardware transactional memory
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int64_t htmTransactionStarts;
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int64_t htmTransactionStops;
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// constructor: initialize SimpleThread from given process structure
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// FS
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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BaseMMU *_mmu, BaseISA *_isa);
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// SE
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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Process *_process, BaseMMU *_mmu,
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BaseISA *_isa);
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virtual ~SimpleThread() {}
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void takeOverFrom(ThreadContext *oldContext) override;
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void copyState(ThreadContext *oldContext);
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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/***************************************************************
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* SimpleThread functions to provide CPU with access to various
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* state.
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**************************************************************/
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/** Returns the pointer to this SimpleThread's ThreadContext. Used
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* when a ThreadContext must be passed to objects outside of the
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* CPU.
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*/
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ThreadContext *getTC() { return this; }
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void
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demapPage(Addr vaddr, uint64_t asn)
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{
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mmu->demapPage(vaddr, asn);
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}
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/*******************************************
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* ThreadContext interface functions.
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******************************************/
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bool schedule(PCEvent *e) override { return pcEventQueue.schedule(e); }
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bool remove(PCEvent *e) override { return pcEventQueue.remove(e); }
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void
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scheduleInstCountEvent(Event *event, Tick count) override
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{
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comInstEventQueue.schedule(event, count);
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}
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void
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descheduleInstCountEvent(Event *event) override
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{
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comInstEventQueue.deschedule(event);
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}
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Tick
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getCurrentInstCount() override
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{
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return comInstEventQueue.getCurTick();
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}
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BaseCPU *getCpuPtr() override { return baseCpu; }
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int cpuId() const override { return ThreadState::cpuId(); }
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uint32_t socketId() const override { return ThreadState::socketId(); }
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int threadId() const override { return ThreadState::threadId(); }
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void setThreadId(int id) override { ThreadState::setThreadId(id); }
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ContextID contextId() const override { return ThreadState::contextId(); }
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void setContextId(ContextID id) override { ThreadState::setContextId(id); }
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BaseMMU *getMMUPtr() override { return mmu; }
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CheckerCPU *getCheckerCpuPtr() override { return NULL; }
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BaseISA *getIsaPtr() override { return isa; }
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TheISA::Decoder *getDecoderPtr() override { return &decoder; }
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System *getSystemPtr() override { return system; }
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Process *getProcessPtr() override { return ThreadState::getProcessPtr(); }
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void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
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Status status() const override { return _status; }
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void setStatus(Status newStatus) override { _status = newStatus; }
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/// Set the status to Active.
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void activate() override;
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/// Set the status to Suspended.
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void suspend() override;
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/// Set the status to Halted.
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void halt() override;
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Tick
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readLastActivate() override
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{
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return ThreadState::readLastActivate();
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}
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Tick
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readLastSuspend() override
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{
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return ThreadState::readLastSuspend();
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}
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void copyArchRegs(ThreadContext *tc) override;
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void
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clearArchRegs() override
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{
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_pcState = 0;
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std::fill(intRegs.begin(), intRegs.end(), 0);
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std::fill(floatRegs.begin(), floatRegs.end(), 0);
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for (auto &vec_reg: vecRegs)
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vec_reg.zero();
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for (auto &pred_reg: vecPredRegs)
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pred_reg.reset();
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std::fill(ccRegs.begin(), ccRegs.end(), 0);
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isa->clear();
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}
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//
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// New accessors for new decoder.
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//
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RegVal
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readIntReg(RegIndex reg_idx) const override
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{
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int flatIndex = isa->flattenIntIndex(reg_idx);
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assert(flatIndex < intRegs.size());
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uint64_t regVal = readIntRegFlat(flatIndex);
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DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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RegVal
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readFloatReg(RegIndex reg_idx) const override
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{
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int flatIndex = isa->flattenFloatIndex(reg_idx);
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assert(flatIndex < floatRegs.size());
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RegVal regVal = readFloatRegFlat(flatIndex);
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DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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const TheISA::VecRegContainer&
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readVecReg(const RegId& reg) const override
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < vecRegs.size());
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const TheISA::VecRegContainer& regVal = readVecRegFlat(flatIndex);
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DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
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reg.index(), flatIndex, regVal);
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return regVal;
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}
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TheISA::VecRegContainer&
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getWritableVecReg(const RegId& reg) override
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < vecRegs.size());
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TheISA::VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
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DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
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reg.index(), flatIndex, regVal);
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return regVal;
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}
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const TheISA::VecElem &
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readVecElem(const RegId ®) const override
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{
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int flatIndex = isa->flattenVecElemIndex(reg.index());
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assert(flatIndex < vecRegs.size());
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const TheISA::VecElem& regVal =
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readVecElemFlat(flatIndex, reg.elemIndex());
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DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
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" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
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return regVal;
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}
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const TheISA::VecPredRegContainer &
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readVecPredReg(const RegId ®) const override
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{
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int flatIndex = isa->flattenVecPredIndex(reg.index());
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assert(flatIndex < vecPredRegs.size());
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const TheISA::VecPredRegContainer& regVal =
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readVecPredRegFlat(flatIndex);
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DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
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reg.index(), flatIndex, regVal);
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return regVal;
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}
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TheISA::VecPredRegContainer &
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getWritableVecPredReg(const RegId ®) override
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{
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int flatIndex = isa->flattenVecPredIndex(reg.index());
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assert(flatIndex < vecPredRegs.size());
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TheISA::VecPredRegContainer& regVal =
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getWritableVecPredRegFlat(flatIndex);
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DPRINTF(VecPredRegs,
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"Reading predicate reg %d (%d) as %s for modify.\n",
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reg.index(), flatIndex, regVal);
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return regVal;
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}
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RegVal
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readCCReg(RegIndex reg_idx) const override
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{
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int flatIndex = isa->flattenCCIndex(reg_idx);
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assert(0 <= flatIndex);
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assert(flatIndex < ccRegs.size());
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uint64_t regVal(readCCRegFlat(flatIndex));
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DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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void
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setIntReg(RegIndex reg_idx, RegVal val) override
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{
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int flatIndex = isa->flattenIntIndex(reg_idx);
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assert(flatIndex < intRegs.size());
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DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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setIntRegFlat(flatIndex, val);
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}
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void
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setFloatReg(RegIndex reg_idx, RegVal val) override
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{
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int flatIndex = isa->flattenFloatIndex(reg_idx);
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assert(flatIndex < floatRegs.size());
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// XXX: Fix array out of bounds compiler error for gem5.fast
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// when checkercpu enabled
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if (flatIndex < floatRegs.size())
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setFloatRegFlat(flatIndex, val);
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DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
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reg_idx, flatIndex, val);
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}
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void
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setVecReg(const RegId ®, const TheISA::VecRegContainer &val) override
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < vecRegs.size());
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setVecRegFlat(flatIndex, val);
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DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
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reg.index(), flatIndex, val);
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}
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void
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setVecElem(const RegId ®, const TheISA::VecElem &val) override
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{
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int flatIndex = isa->flattenVecElemIndex(reg.index());
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assert(flatIndex < vecRegs.size());
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setVecElemFlat(flatIndex, reg.elemIndex(), val);
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DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
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" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
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}
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void
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setVecPredReg(const RegId ®,
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const TheISA::VecPredRegContainer &val) override
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{
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int flatIndex = isa->flattenVecPredIndex(reg.index());
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assert(flatIndex < vecPredRegs.size());
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setVecPredRegFlat(flatIndex, val);
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DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n",
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reg.index(), flatIndex, val);
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}
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void
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setCCReg(RegIndex reg_idx, RegVal val) override
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{
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int flatIndex = isa->flattenCCIndex(reg_idx);
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assert(flatIndex < ccRegs.size());
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DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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setCCRegFlat(flatIndex, val);
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}
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TheISA::PCState pcState() const override { return _pcState; }
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void pcState(const TheISA::PCState &val) override { _pcState = val; }
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void
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pcStateNoRecord(const TheISA::PCState &val) override
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{
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_pcState = val;
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}
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Addr instAddr() const override { return _pcState.instAddr(); }
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Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
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MicroPC microPC() const override { return _pcState.microPC(); }
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bool readPredicate() const { return predicate; }
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void setPredicate(bool val) { predicate = val; }
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RegVal
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readMiscRegNoEffect(RegIndex misc_reg) const override
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{
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return isa->readMiscRegNoEffect(misc_reg);
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}
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RegVal
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readMiscReg(RegIndex misc_reg) override
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{
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return isa->readMiscReg(misc_reg);
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}
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void
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setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
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{
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return isa->setMiscRegNoEffect(misc_reg, val);
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}
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void
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setMiscReg(RegIndex misc_reg, RegVal val) override
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{
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return isa->setMiscReg(misc_reg, val);
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}
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RegId
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flattenRegId(const RegId& regId) const override
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{
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return isa->flattenRegId(regId);
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}
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unsigned readStCondFailures() const override { return storeCondFailures; }
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bool
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readMemAccPredicate()
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{
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return memAccPredicate;
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}
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void
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setMemAccPredicate(bool val)
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{
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memAccPredicate = val;
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}
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void
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setStCondFailures(unsigned sc_failures) override
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{
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storeCondFailures = sc_failures;
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}
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RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
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void
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setIntRegFlat(RegIndex idx, RegVal val) override
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{
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intRegs[idx] = val;
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}
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RegVal
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readFloatRegFlat(RegIndex idx) const override
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{
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return floatRegs[idx];
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}
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void
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setFloatRegFlat(RegIndex idx, RegVal val) override
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{
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floatRegs[idx] = val;
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}
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const TheISA::VecRegContainer &
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readVecRegFlat(RegIndex reg) const override
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{
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return vecRegs[reg];
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}
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TheISA::VecRegContainer &
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getWritableVecRegFlat(RegIndex reg) override
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{
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return vecRegs[reg];
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}
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void
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setVecRegFlat(RegIndex reg, const TheISA::VecRegContainer &val) override
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|
{
|
|
vecRegs[reg] = val;
|
|
}
|
|
|
|
const TheISA::VecElem &
|
|
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
|
|
{
|
|
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
|
|
}
|
|
|
|
void
|
|
setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
|
|
const TheISA::VecElem &val) override
|
|
{
|
|
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
|
|
}
|
|
|
|
const TheISA::VecPredRegContainer &
|
|
readVecPredRegFlat(RegIndex reg) const override
|
|
{
|
|
return vecPredRegs[reg];
|
|
}
|
|
|
|
TheISA::VecPredRegContainer &
|
|
getWritableVecPredRegFlat(RegIndex reg) override
|
|
{
|
|
return vecPredRegs[reg];
|
|
}
|
|
|
|
void
|
|
setVecPredRegFlat(RegIndex reg,
|
|
const TheISA::VecPredRegContainer &val) override
|
|
{
|
|
vecPredRegs[reg] = val;
|
|
}
|
|
|
|
RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
|
|
void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
|
|
|
|
// hardware transactional memory
|
|
void htmAbortTransaction(uint64_t htm_uid,
|
|
HtmFailureFaultCause cause) override;
|
|
|
|
BaseHTMCheckpointPtr& getHtmCheckpointPtr() override;
|
|
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
|
|
};
|
|
|
|
} // namespace gem5
|
|
|
|
#endif // __CPU_SIMPLE_THREAD_HH__
|