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a41e1320077fc12869827899d034d5e3de155ffd
gem5/src/arch
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Gabe Black a41e132007 ARM: Make native trace only print when registers are changing value.
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
2009-07-27 00:52:01 -07:00
..
alpha
Alpha: Missed a file in an earlier changeset.
2009-07-09 00:20:41 -07:00
arm
ARM: Make native trace only print when registers are changing value.
2009-07-27 00:52:01 -07:00
mips
MIPS: Small fix I forgot to qrefresh into my last change.
2009-07-22 01:57:55 -07:00
sparc
SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
2009-07-25 15:14:00 -07:00
x86
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
2009-07-19 23:54:56 -07:00
isa_parser.py
isa_parser: Get rid of the now unused ControlBitfieldOperand.
2009-07-20 20:20:17 -07:00
isa_specific.hh
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
2008-09-10 14:26:15 -04:00
micro_asm_test.py
Add a second section to make sure the ROM is extended properly.
2007-05-31 22:21:21 +00:00
micro_asm.py
Microcode: Fix a silent typo error in the microcode assembler.
2008-10-09 00:07:38 -07:00
SConscript
Registers: Add a registers.hh file as an ISA switched header.
2009-07-08 23:02:21 -07:00
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