569 lines
20 KiB
Plaintext
569 lines
20 KiB
Plaintext
// Copyright (c) 2007 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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////////////////////////////////////////////////////////////////////
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//
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// Decode the one byte opcodes
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//
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0x1: decode OPCODE_OP_TOP5 {
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format WarnUnimpl {
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0x00: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: push_ES();
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}
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: pop_ES();
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}
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default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x01: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: push_CS();
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}
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//Any time this is seen, it should generate a two byte opcode
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0x7: M5InternalError::error(
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{{"Saw a one byte opcode whose value was 0x0F!"}});
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default: MultiInst::OR(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x02: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: push_SS();
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}
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: pop_SS();
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}
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default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x03: decode OPCODE_OP_BOTTOM3 {
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: push_DS();
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}
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: pop_DS();
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}
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default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x04: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the ES segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: daa();
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}
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default: MultiInst::AND(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x05: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the CS segment override prefix!"}});
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0x7: das();
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default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the SS segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: aaa();
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}
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default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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0x07: decode OPCODE_OP_BOTTOM3 {
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0x6: M5InternalError::error(
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{{"Tried to execute the DS segment override prefix!"}});
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: aas();
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}
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default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
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[Eb,Gb], [Ev,Gv],
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[Gb,Eb], [Gv,Ev],
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[rAb,Ib], [rAv,Iz]);
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}
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format Inst {
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0x08: decode MODE_SUBMODE {
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0x0: M5InternalError::error (
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{{"Tried to execute an REX prefix!"}});
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default: INC(Bv);
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}
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0x09: decode MODE_SUBMODE {
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0x0: M5InternalError::error (
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{{"Tried to execute an REX prefix!"}});
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default: DEC(Bv);
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}
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0x0A: PUSH(Bv);
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0x0B: POP(Bv);
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}
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0x0C: decode OPCODE_OP_BOTTOM3 {
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0x0: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: Inst::PUSHA();
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}
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0x1: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: Inst::POPA();
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}
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0x2: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: bound_Gv_Ma();
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}
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0x3: decode MODE_SUBMODE {
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//The second operand should really be of size "d", but it's
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//set to "v" in order to have a consistent register size.
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//This shouldn't affect behavior.
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0x0: Inst::MOVSXD(Gv,Ev);
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default: arpl_Ew_Gw();
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}
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0x4: M5InternalError::error(
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{{"Tried to execute the FS segment override prefix!"}});
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0x5: M5InternalError::error(
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{{"Tried to execute the GS segment override prefix!"}});
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0x6: M5InternalError::error(
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{{"Tried to execute the operand size override prefix!"}});
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0x7: M5InternalError::error(
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{{"Tried to execute the DS address size override prefix!"}});
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}
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0x0D: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::PUSH(Iz);
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0x1: Inst::IMUL(Gv,Ev,Iz);
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0x2: Inst::PUSH(Ib);
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0x3: Inst::IMUL(Gv,Ev,Ib);
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0x4: ins_Yb_Dx();
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0x5: ins_Yz_Dx();
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0x6: outs_Dx_Xb();
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0x7: outs_Dx_Xz();
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}
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format Inst {
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0x0E: decode OPCODE_OP_BOTTOM3 {
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0x0: JO(Jb);
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0x1: JNO(Jb);
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0x2: JB(Jb);
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0x3: JNB(Jb);
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0x4: JZ(Jb);
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0x5: JNZ(Jb);
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0x6: JBE(Jb);
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0x7: JNBE(Jb);
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}
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0x0F: decode OPCODE_OP_BOTTOM3 {
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0x0: JS(Jb);
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0x1: JNS(Jb);
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0x2: JP(Jb);
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0x3: JNP(Jb);
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0x4: JL(Jb);
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0x5: JNL(Jb);
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0x6: JLE(Jb);
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0x7: JNLE(Jb);
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}
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}
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format Inst {
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0x10: decode OPCODE_OP_BOTTOM3 {
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//0x0: group1_Eb_Ib();
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0x0: decode MODRM_REG {
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0x0: ADD(Eb,Ib);
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0x1: OR(Eb,Ib);
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0x2: ADC(Eb,Ib);
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0x3: SBB(Eb,Ib);
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0x4: AND(Eb,Ib);
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0x5: SUB(Eb,Ib);
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0x6: XOR(Eb,Ib);
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0x7: CMP(Eb,Ib);
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}
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//0x1: group1_Ev_Iz();
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0x1: decode MODRM_REG {
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0x0: ADD(Ev,Iz);
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0x1: OR(Ev,Iz);
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0x2: ADC(Ev,Iz);
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0x3: SBB(Ev,Iz);
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0x4: AND(Ev,Iz);
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0x5: SUB(Ev,Iz);
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0x6: XOR(Ev,Iz);
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0x7: CMP(Ev,Iz);
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}
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0x2: decode MODE_SUBMODE {
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0x0: UD2();
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//default: group1_Eb_Ib();
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default: decode MODRM_REG {
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0x0: ADD(Eb,Ib);
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0x1: OR(Eb,Ib);
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0x2: ADC(Eb,Ib);
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0x3: SBB(Eb,Ib);
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0x4: AND(Eb,Ib);
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0x5: SUB(Eb,Ib);
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0x6: XOR(Eb,Ib);
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0x7: CMP(Eb,Ib);
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}
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}
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//0x3: group1_Ev_Ib();
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0x3: decode MODRM_REG {
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0x0: ADD(Ev,Ib);
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0x1: OR(Ev,Ib);
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0x2: ADC(Ev,Ib);
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0x3: SBB(Ev,Ib);
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0x4: AND(Ev,Ib);
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0x5: SUB(Ev,Ib);
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0x6: XOR(Ev,Ib);
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0x7: CMP(Ev,Ib);
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}
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0x4: TEST(Eb,Gb);
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0x5: TEST(Ev,Gv);
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0x6: XCHG(Eb,Gb);
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0x7: XCHG(Ev,Gv);
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}
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}
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0x11: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::MOV(Eb,Gb);
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0x1: Inst::MOV(Ev,Gv);
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0x2: Inst::MOV(Gb,Eb);
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0x3: Inst::MOV(Gv,Ev);
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0x4: mov_MwRv_Sw(); //What to do with this one?
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0x5: Inst::LEA(Gv,M);
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0x6: mov_Sw_MwRv();
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0x7: group10_Ev(); //Make sure this is Ev
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}
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0x12: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::NOP(); //XXX repe makes this a "pause"
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default: xchg_B_rAX();
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}
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0x13: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::CDQE(rAv);
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0x1: Inst::CQO(rAv,rDv);
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0x2: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: call_far_Ap();
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}
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0x3: fwait(); //aka wait
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0x4: pushf_Fv();
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0x5: popf_Fv();
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//Both of these should be illegal only if CPUID.AHF64=0,
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//according to sandpile.org
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: sahf();
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}
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0x7: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: lahf();
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}
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}
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0x14: decode OPCODE_OP_BOTTOM3 {
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0x0: mov_Al_Ob();
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0x1: mov_rAX_Ov();
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0x2: mov_Ob_Al();
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0x3: mov_Ov_rAX();
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0x4: movs_Yb_Xb();
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0x5: movs_Yv_Xv();
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0x6: cmps_Yb_Xb();
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0x7: cmps_Yv_Xv();
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}
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0x15: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::TEST(rAb,Ib);
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0x1: Inst::TEST(rAv,Iz);
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0x2: stos_Yb_Al();
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0x3: stos_Yv_rAX();
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0x4: lods_Al_Xb();
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0x5: lods_rAX_Xv();
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0x6: scas_Yb_Al();
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0x7: scas_Yv_rAX();
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}
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format Inst {
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0x16: MOV(Bb,Ib);
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0x17: MOV(Bv,Iv);
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0x18: decode OPCODE_OP_BOTTOM3 {
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//0x0: group2_Eb_Ib();
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0x0: decode MODRM_REG {
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0x0: ROL(Eb,Ib);
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0x1: ROR(Eb,Ib);
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0x2: RCL(Eb,Ib);
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0x3: RCR(Eb,Ib);
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0x4: SAL(Eb,Ib);
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0x5: SHR(Eb,Ib);
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0x6: SAL(Eb,Ib);
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0x7: SAR(Eb,Ib);
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}
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//0x1: group2_Ev_Ib();
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0x1: decode MODRM_REG {
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0x0: ROL(Ev,Ib);
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0x1: ROR(Ev,Ib);
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0x2: RCL(Ev,Ib);
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0x3: RCR(Ev,Ib);
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0x4: SAL(Ev,Ib);
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0x5: SHR(Ev,Ib);
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0x6: SAL(Ev,Ib);
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0x7: SAR(Ev,Ib);
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}
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0x2: RET_NEAR(Iw);
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0x3: RET_NEAR();
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0x4: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::les_Gz_Mp();
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}
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0x5: decode MODE_SUBMODE {
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0x0: UD2();
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default: WarnUnimpl::lds_Gz_Mp();
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}
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//0x6: group12_Eb_Ib();
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0x6: decode MODRM_REG {
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0x0: MOV(Eb,Ib);
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default: UD2();
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}
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//0x7: group12_Ev_Iz();
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0x7: decode MODRM_REG {
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0x0: MOV(Ev,Iz);
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default: UD2();
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}
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}
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}
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0x19: decode OPCODE_OP_BOTTOM3 {
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0x0: enter_Iw_Ib();
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0x1: Inst::LEAVE();
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0x2: ret_far_Iw();
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0x3: ret_far();
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0x4: int3();
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0x5: int_Ib();
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0x6: decode MODE_SUBMODE {
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0x0: Inst::UD2();
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default: into();
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}
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0x7: iret();
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}
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0x1A: decode OPCODE_OP_BOTTOM3 {
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format Inst {
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//0x0: group2_Eb_1();
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0x0: decode MODRM_REG {
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0x0: ROL_1(Eb);
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0x1: ROR_1(Eb);
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0x2: RCL_1(Eb);
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0x3: RCR_1(Eb);
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0x4: SAL_1(Eb);
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0x5: SHR_1(Eb);
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0x6: SAL_1(Eb);
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0x7: SAR_1(Eb);
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}
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//0x1: group2_Ev_1();
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0x1: decode MODRM_REG {
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0x0: ROL_1(Ev);
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0x1: ROR_1(Ev);
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0x2: RCL_1(Ev);
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0x3: RCR_1(Ev);
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0x4: SAL_1(Ev);
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0x5: SHR_1(Ev);
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0x6: SAL_1(Ev);
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0x7: SAR_1(Ev);
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}
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//0x2: group2_Eb_Cl();
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0x2: decode MODRM_REG {
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0x0: ROL(Eb,rCb);
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0x1: ROR(Eb,rCb);
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0x2: RCL(Eb,rCb);
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0x3: RCR(Eb,rCb);
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0x4: SAL(Eb,rCb);
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0x5: SHR(Eb,rCb);
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0x6: SAL(Eb,rCb);
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0x7: SAR(Eb,rCb);
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}
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//The second operand should have size "b", but to have
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//consistent register sizes it's "v". This shouldn't have
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//any affect on functionality.
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//0x3: group2_Ev_Cl();
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0x3: decode MODRM_REG {
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0x0: ROL(Ev,rCv);
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0x1: ROR(Ev,rCv);
|
|
0x2: RCL(Ev,rCv);
|
|
0x3: RCR(Ev,rCv);
|
|
0x4: SAL(Ev,rCv);
|
|
0x5: SHR(Ev,rCv);
|
|
0x6: SAL(Ev,rCv);
|
|
0x7: SAR(Ev,rCv);
|
|
}
|
|
}
|
|
0x4: decode MODE_SUBMODE {
|
|
0x0: Inst::UD2();
|
|
default: aam_Ib();
|
|
}
|
|
0x5: decode MODE_SUBMODE {
|
|
0x0: Inst::UD2();
|
|
default: aad_Ib();
|
|
}
|
|
0x6: decode MODE_SUBMODE {
|
|
0x0: Inst::UD2();
|
|
default: salc();
|
|
}
|
|
0x7: xlat();
|
|
}
|
|
0x1B: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: esc0();
|
|
0x1: esc1();
|
|
0x2: esc2();
|
|
0x3: esc3();
|
|
0x4: esc4();
|
|
0x5: esc5();
|
|
0x6: esc6();
|
|
0x7: esc7();
|
|
}
|
|
0x1C: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: loopne_Jb();
|
|
0x1: loope_Jb();
|
|
0x2: loop_Jb();
|
|
0x3: jcxz_or_jecx_or_jrcx();
|
|
0x4: in_Al_Ib();
|
|
0x5: in_eAX_Ib();
|
|
0x6: out_Ib_Al();
|
|
0x7: out_Ib_eAX();
|
|
}
|
|
0x1D: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: Inst::CALL_NEAR(Jz);
|
|
0x1: Inst::JMP(Jz);
|
|
0x2: decode MODE_SUBMODE {
|
|
0x0: Inst::UD2();
|
|
default: jmp_far_Ap();
|
|
}
|
|
0x3: Inst::JMP(Jb);
|
|
0x4: in_Al_Dx();
|
|
0x5: in_eAX_Dx();
|
|
0x6: out_Dx_Al();
|
|
0x7: out_Dx_eAX();
|
|
}
|
|
0x1E: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: M5InternalError::error(
|
|
{{"Tried to execute the lock prefix!"}});
|
|
0x1: int1();
|
|
0x2: M5InternalError::error(
|
|
{{"Tried to execute the repne prefix!"}});
|
|
0x3: M5InternalError::error(
|
|
{{"Tried to execute the rep/repe prefix!"}});
|
|
0x4: hlt();
|
|
0x5: cmc();
|
|
//0x6: group3_Eb();
|
|
0x6: decode MODRM_REG {
|
|
0x0: Inst::TEST(Eb,Iz);
|
|
0x1: Inst::TEST(Eb,Iz);
|
|
0x2: Inst::NOT(Eb);
|
|
0x3: Inst::NEG(Eb);
|
|
0x4: Inst::MUL_B(Eb);
|
|
0x5: Inst::IMUL_B(Eb);
|
|
0x6: div_Eb();
|
|
0x7: idiv_Eb();
|
|
}
|
|
//0x7: group3_Ev();
|
|
0x7: decode MODRM_REG {
|
|
0x0: Inst::TEST(Ev,Iz);
|
|
0x1: Inst::TEST(Ev,Iz);
|
|
0x2: Inst::NOT(Ev);
|
|
0x3: Inst::NEG(Ev);
|
|
0x4: Inst::MUL(Ev);
|
|
0x5: Inst::IMUL(Ev);
|
|
0x6: div_Ev();
|
|
0x7: idiv_Ev();
|
|
}
|
|
}
|
|
0x1F: decode OPCODE_OP_BOTTOM3 {
|
|
0x0: clc();
|
|
0x1: stc();
|
|
0x2: cli();
|
|
0x3: sti();
|
|
0x4: cld();
|
|
0x5: std();
|
|
format Inst {
|
|
//0x6: group4();
|
|
0x6: decode MODRM_REG {
|
|
0x0: INC(Eb);
|
|
0x1: DEC(Eb);
|
|
default: UD2();
|
|
}
|
|
//0x7: group5();
|
|
0x7: decode MODRM_REG {
|
|
0x0: INC(Ev);
|
|
0x1: DEC(Ev);
|
|
0x2: CALL_NEAR(Ev);
|
|
0x3: WarnUnimpl::call_far_Mp();
|
|
0x4: JMP(Ev);
|
|
0x5: WarnUnimpl::jmp_far_Mp();
|
|
0x6: PUSH(Ev);
|
|
0x7: UD2();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
default: FailUnimpl::oneByteOps();
|
|
}
|