a8b9bc4770
These were left over from when these were template classes. Change-Id: I102d2016fbba0ca09f16e10d8741ae0e2f967681 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52484 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
350 lines
12 KiB
C++
350 lines
12 KiB
C++
/*
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* Copyright (c) 2016-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_FREE_LIST_HH__
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#define __CPU_O3_FREE_LIST_HH__
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#include <iostream>
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#include <queue>
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#include "base/logging.hh"
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#include "base/trace.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/regfile.hh"
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#include "debug/FreeList.hh"
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namespace gem5
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{
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namespace o3
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{
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class UnifiedRenameMap;
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/**
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* Free list for a single class of registers (e.g., integer
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* or floating point). Because the register class is implicitly
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* determined by the rename map instance being accessed, all
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* architectural register index parameters and values in this class
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* are relative (e.g., %fp2 is just index 2).
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*/
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class SimpleFreeList
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{
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private:
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/** The actual free list */
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std::queue<PhysRegIdPtr> freeRegs;
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public:
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SimpleFreeList() {};
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/** Add a physical register to the free list */
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void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); }
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/** Add physical registers to the free list */
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template<class InputIt>
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void
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addRegs(InputIt first, InputIt last) {
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std::for_each(first, last, [this](typename InputIt::value_type& reg) {
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freeRegs.push(®);
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});
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}
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/** Get the next available register from the free list */
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PhysRegIdPtr getReg()
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{
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assert(!freeRegs.empty());
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PhysRegIdPtr free_reg = freeRegs.front();
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freeRegs.pop();
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return free_reg;
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}
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/** Return the number of free registers on the list. */
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unsigned numFreeRegs() const { return freeRegs.size(); }
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/** True iff there are free registers on the list. */
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bool hasFreeRegs() const { return !freeRegs.empty(); }
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};
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/**
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* FreeList class that simply holds the list of free integer and floating
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* point registers. Can request for a free register of either type, and
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* also send back free registers of either type. This is a very simple
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* class, but it should be sufficient for most implementations. Like all
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* other classes, it assumes that the indices for the floating point
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* registers starts after the integer registers end. Hence the variable
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* numPhysicalIntRegs is logically equivalent to the baseFP dependency.
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* Note that while this most likely should be called FreeList, the name
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* "FreeList" is used in a typedef within the CPU Policy, and therefore no
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* class can be named simply "FreeList".
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* @todo: Give a better name to the base FP dependency.
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*/
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class UnifiedFreeList
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{
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private:
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/** The object name, for DPRINTF. We have to declare this
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* explicitly because Scoreboard is not a SimObject. */
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const std::string _name;
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/** The list of free integer registers. */
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SimpleFreeList intList;
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/** The list of free floating point registers. */
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SimpleFreeList floatList;
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/** The following two are exclusive interfaces. */
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/** @{ */
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/** The list of free vector registers. */
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SimpleFreeList vecList;
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/** The list of free vector element registers. */
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SimpleFreeList vecElemList;
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/** @} */
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/** The list of free predicate registers. */
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SimpleFreeList predList;
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/** The list of free condition-code registers. */
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SimpleFreeList ccList;
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/**
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* The register file object is used only to distinguish integer
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* from floating-point physical register indices.
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*/
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PhysRegFile *regFile;
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/*
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* We give UnifiedRenameMap internal access so it can get at the
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* internal per-class free lists and associate those with its
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* per-class rename maps. See UnifiedRenameMap::init().
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*/
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friend class UnifiedRenameMap;
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public:
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/** Constructs a free list.
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* @param _numPhysicalIntRegs Number of physical integer registers.
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* @param reservedIntRegs Number of integer registers already
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* used by initial mappings.
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* @param _numPhysicalFloatRegs Number of physical fp registers.
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* @param reservedFloatRegs Number of fp registers already
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* used by initial mappings.
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*/
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UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile);
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/** Gives the name of the freelist. */
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std::string name() const { return _name; };
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/** Returns a pointer to the condition-code free list */
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SimpleFreeList *getCCList() { return &ccList; }
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/** Gets a free integer register. */
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PhysRegIdPtr getIntReg() { return intList.getReg(); }
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/** Gets a free fp register. */
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PhysRegIdPtr getFloatReg() { return floatList.getReg(); }
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/** Gets a free vector register. */
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PhysRegIdPtr getVecReg() { return vecList.getReg(); }
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/** Gets a free vector elemenet register. */
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PhysRegIdPtr getVecElem() { return vecElemList.getReg(); }
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/** Gets a free predicate register. */
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PhysRegIdPtr getVecPredReg() { return predList.getReg(); }
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/** Gets a free cc register. */
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PhysRegIdPtr getCCReg() { return ccList.getReg(); }
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/** Adds a register back to the free list. */
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void addReg(PhysRegIdPtr freed_reg);
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/** Adds a register back to the free list. */
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template<class InputIt>
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void addRegs(InputIt first, InputIt last);
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/** Adds an integer register back to the free list. */
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void addIntReg(PhysRegIdPtr freed_reg) { intList.addReg(freed_reg); }
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/** Adds a fp register back to the free list. */
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void addFloatReg(PhysRegIdPtr freed_reg) { floatList.addReg(freed_reg); }
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/** Adds a vector register back to the free list. */
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void addVecReg(PhysRegIdPtr freed_reg) { vecList.addReg(freed_reg); }
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/** Adds a vector element register back to the free list. */
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void addVecElem(PhysRegIdPtr freed_reg) {
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vecElemList.addReg(freed_reg);
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}
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/** Adds a predicate register back to the free list. */
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void addVecPredReg(PhysRegIdPtr freed_reg) { predList.addReg(freed_reg); }
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/** Adds a cc register back to the free list. */
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void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }
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/** Checks if there are any free integer registers. */
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bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
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/** Checks if there are any free fp registers. */
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bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }
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/** Checks if there are any free vector registers. */
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bool hasFreeVecRegs() const { return vecList.hasFreeRegs(); }
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/** Checks if there are any free vector registers. */
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bool hasFreeVecElems() const { return vecElemList.hasFreeRegs(); }
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/** Checks if there are any free predicate registers. */
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bool hasFreeVecPredRegs() const { return predList.hasFreeRegs(); }
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/** Checks if there are any free cc registers. */
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bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
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/** Returns the number of free integer registers. */
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unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
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/** Returns the number of free fp registers. */
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unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }
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/** Returns the number of free vector registers. */
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unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }
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/** Returns the number of free vector registers. */
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unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }
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/** Returns the number of free predicate registers. */
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unsigned numFreeVecPredRegs() const { return predList.numFreeRegs(); }
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/** Returns the number of free cc registers. */
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unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
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};
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template<class InputIt>
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inline void
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UnifiedFreeList::addRegs(InputIt first, InputIt last)
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{
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// Are there any registers to add?
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if (first == last)
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return;
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panic_if((first != last) &&
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first->classValue() != (last-1)->classValue(),
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"Attempt to add mixed type regs: %s and %s",
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first->className(),
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(last-1)->className());
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switch (first->classValue()) {
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case IntRegClass:
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intList.addRegs(first, last);
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break;
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case FloatRegClass:
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floatList.addRegs(first, last);
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break;
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case VecRegClass:
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vecList.addRegs(first, last);
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break;
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case VecElemClass:
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vecElemList.addRegs(first, last);
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break;
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case VecPredRegClass:
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predList.addRegs(first, last);
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break;
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case CCRegClass:
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ccList.addRegs(first, last);
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break;
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default:
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panic("Unexpected RegClass (%s)",
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first->className());
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}
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}
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inline void
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UnifiedFreeList::addReg(PhysRegIdPtr freed_reg)
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{
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DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->index(),
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freed_reg->className());
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//Might want to add in a check for whether or not this register is
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//already in there. A bit vector or something similar would be useful.
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switch (freed_reg->classValue()) {
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case IntRegClass:
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intList.addReg(freed_reg);
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break;
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case FloatRegClass:
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floatList.addReg(freed_reg);
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break;
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case VecRegClass:
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vecList.addReg(freed_reg);
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break;
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case VecElemClass:
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vecElemList.addReg(freed_reg);
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break;
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case VecPredRegClass:
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predList.addReg(freed_reg);
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break;
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case CCRegClass:
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ccList.addReg(freed_reg);
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break;
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default:
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panic("Unexpected RegClass (%s)",
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freed_reg->className());
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}
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// These assert conditions ensure that the number of free
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// registers are not more than the # of total Physical Registers.
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// If this were false, it would mean that registers
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// have been freed twice, overflowing the free register
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// pool and potentially crashing SMT workloads.
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// ----
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// Comment out for now so as to not potentially break
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// CMP and single-threaded workloads
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// ----
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// assert(freeIntRegs.size() <= numPhysicalIntRegs);
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// assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
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}
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} // namespace o3
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} // namespace gem5
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#endif // __CPU_O3_FREE_LIST_HH__
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