9fff55c93c
This is a way to send a very generic poke to the workload so it can do something. It's up to the workload to know what information to look for to interpret an event, such as what PC it came from, what register values are, or the context of the workload itself (is this SE mode? which OS is running?). Change-Id: Ifa4bdf3b5c5a934338c50600747d0b65f4b5eb2b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34162 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
286 lines
8.6 KiB
C++
286 lines
8.6 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SIM_PSEUDO_INST_HH__
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#define __SIM_PSEUDO_INST_HH__
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#include <gem5/asm/generic/m5ops.h>
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class ThreadContext;
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#include "arch/pseudo_inst.hh"
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#include "arch/utility.hh"
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#include "base/bitfield.hh"
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#include "base/types.hh" // For Tick and Addr data types.
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#include "debug/PseudoInst.hh"
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#include "sim/guest_abi.hh"
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struct PseudoInstABI
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{
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using State = int;
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};
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namespace GuestABI
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{
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template <>
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struct Argument<PseudoInstABI, uint64_t>
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{
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static uint64_t
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get(ThreadContext *tc, PseudoInstABI::State &state)
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{
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uint64_t result =
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TheISA::getArgument(tc, state, sizeof(uint64_t), false);
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state++;
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return result;
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}
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};
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} // namespace GuestABI
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namespace PseudoInst
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{
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static inline void
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decodeAddrOffset(Addr offset, uint8_t &func)
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{
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func = bits(offset, 15, 8);
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}
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void arm(ThreadContext *tc);
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void quiesce(ThreadContext *tc);
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void quiesceSkip(ThreadContext *tc);
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void quiesceNs(ThreadContext *tc, uint64_t ns);
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void quiesceCycles(ThreadContext *tc, uint64_t cycles);
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uint64_t quiesceTime(ThreadContext *tc);
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uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
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uint64_t offset);
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uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
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uint64_t offset, Addr filenameAddr);
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void loadsymbol(ThreadContext *xc);
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void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
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uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
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uint64_t rpns(ThreadContext *tc);
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void wakeCPU(ThreadContext *tc, uint64_t cpuid);
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void m5exit(ThreadContext *tc, Tick delay);
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void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
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uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c,
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uint64_t d, uint64_t e, uint64_t f);
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void resetstats(ThreadContext *tc, Tick delay, Tick period);
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void dumpstats(ThreadContext *tc, Tick delay, Tick period);
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void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
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void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
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void debugbreak(ThreadContext *tc);
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void switchcpu(ThreadContext *tc);
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void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
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void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
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void m5Syscall(ThreadContext *tc);
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void togglesync(ThreadContext *tc);
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void triggerWorkloadEvent(ThreadContext *tc);
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/**
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* Execute a decoded M5 pseudo instruction
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*
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* The ISA-specific code is responsible to decode the pseudo inst
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* function number and subfunction number. After that has been done,
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* the rest of the instruction can be implemented in an ISA-agnostic
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* manner using the ISA-specific getArguments functions.
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*
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* @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
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* @param result A reference to a uint64_t to store a result in.
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* @return Whether the pseudo instruction was recognized/handled.
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*/
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template <typename ABI, bool store_ret>
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bool
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pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
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{
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DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
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result = 0;
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switch (func) {
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case M5OP_ARM:
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invokeSimcall<ABI>(tc, arm);
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return true;
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case M5OP_QUIESCE:
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invokeSimcall<ABI>(tc, quiesce);
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return true;
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case M5OP_QUIESCE_NS:
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invokeSimcall<ABI>(tc, quiesceNs);
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return true;
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case M5OP_QUIESCE_CYCLE:
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invokeSimcall<ABI>(tc, quiesceCycles);
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return true;
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case M5OP_QUIESCE_TIME:
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result = invokeSimcall<ABI, store_ret>(tc, quiesceTime);
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return true;
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case M5OP_RPNS:
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result = invokeSimcall<ABI, store_ret>(tc, rpns);
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return true;
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case M5OP_WAKE_CPU:
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invokeSimcall<ABI>(tc, wakeCPU);
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return true;
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case M5OP_EXIT:
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invokeSimcall<ABI>(tc, m5exit);
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return true;
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case M5OP_FAIL:
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invokeSimcall<ABI>(tc, m5fail);
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return true;
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// M5OP_SUM is for sanity checking the gem5 op interface.
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case M5OP_SUM:
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result = invokeSimcall<ABI, store_ret>(tc, m5sum);
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return true;
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case M5OP_INIT_PARAM:
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result = invokeSimcall<ABI, store_ret>(tc, initParam);
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return true;
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case M5OP_LOAD_SYMBOL:
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invokeSimcall<ABI>(tc, loadsymbol);
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return true;
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case M5OP_RESET_STATS:
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invokeSimcall<ABI>(tc, resetstats);
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return true;
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case M5OP_DUMP_STATS:
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invokeSimcall<ABI>(tc, dumpstats);
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return true;
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case M5OP_DUMP_RESET_STATS:
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invokeSimcall<ABI>(tc, dumpresetstats);
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return true;
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case M5OP_CHECKPOINT:
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invokeSimcall<ABI>(tc, m5checkpoint);
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return true;
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case M5OP_WRITE_FILE:
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result = invokeSimcall<ABI, store_ret>(tc, writefile);
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return true;
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case M5OP_READ_FILE:
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result = invokeSimcall<ABI, store_ret>(tc, readfile);
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return true;
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case M5OP_DEBUG_BREAK:
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invokeSimcall<ABI>(tc, debugbreak);
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return true;
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case M5OP_SWITCH_CPU:
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invokeSimcall<ABI>(tc, switchcpu);
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return true;
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case M5OP_ADD_SYMBOL:
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invokeSimcall<ABI>(tc, addsymbol);
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return true;
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case M5OP_PANIC:
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panic("M5 panic instruction called at %s\n", tc->pcState());
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case M5OP_WORK_BEGIN:
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invokeSimcall<ABI>(tc, workbegin);
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return true;
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case M5OP_WORK_END:
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invokeSimcall<ABI>(tc, workend);
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return true;
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case M5OP_RESERVED1:
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case M5OP_RESERVED2:
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case M5OP_RESERVED3:
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case M5OP_RESERVED4:
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case M5OP_RESERVED5:
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warn("Unimplemented m5 op (%#x)\n", func);
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return false;
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/* SE mode functions */
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case M5OP_SE_SYSCALL:
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invokeSimcall<ABI>(tc, m5Syscall);
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return true;
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case M5OP_SE_PAGE_FAULT:
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invokeSimcall<ABI>(tc, TheISA::m5PageFault);
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return true;
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/* dist-gem5 functions */
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case M5OP_DIST_TOGGLE_SYNC:
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invokeSimcall<ABI>(tc, togglesync);
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return true;
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case M5OP_WORKLOAD:
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invokeSimcall<ABI>(tc, triggerWorkloadEvent);
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return true;
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default:
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warn("Unhandled m5 op: %#x\n", func);
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return false;
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}
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}
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template <typename ABI, bool store_ret=false>
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bool
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pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
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{
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return pseudoInstWork<ABI, store_ret>(tc, func, result);
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}
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template <typename ABI, bool store_ret=true>
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bool
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pseudoInst(ThreadContext *tc, uint8_t func)
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{
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uint64_t result;
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return pseudoInstWork<ABI, store_ret>(tc, func, result);
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}
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} // namespace PseudoInst
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#endif // __SIM_PSEUDO_INST_HH__
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