7bc9b0175f
Enable a gem5 system to be an SST::Component.
This change includes,
- SST::gem5Component: responsible for,
- initializing the Python environment for gem5
- instantiating gem5 SimObjects
- connecting SST::SSTResponderSubComponent to
gem5::OutgoingRequestBridge
- hanlding the gem5 event queue (no thread-synchronization)
- handling executing gem5 events
- SST::SSTResponderSubComponent: responsible for,
- receiving gem5 requests and sending the requests to
memory.
- sending responses to the corresponding
gem5::OutgoingRequestBridge.
- SST::SSTResponder: owned by SSTResponderSubComponent, the
actual actor that sends gem5's requests to memory.
- gem5::OutgoingRequestBridge: receives the requests from
gem5 and sends them to SST. This SimObject allows the initialization
requests to be cached and the receiver could query the
initialization data later on.
- gem5::SSTResponderInterface: the interface specifying how SST
communicates with gem5.
- A working example of a gem5/SST setup.
More information is available at ext/sst/README.md.
For installation instructions, please refer to ext/sst/INSTALL.md.
Change-Id: I6b81260ef825415bcfe72b8a078854f4c94de782
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50468
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Using gem5 in an SST simulation
Overview
This directory contains the library needed to use gem5 TimingSimpleCPU model in an SST-driven simulation.
When compiled, the gem5 library for SST libgem5.so will be generated,
containing the libgem5_*.so as well as the gem5 Component and the
SST Responder SubComponent.
On/Off-chip devs TimingSimpleCPU
^ ^ ^
| | |
v v v
==================================== [gem5::NonCoherentXBar]
^ [OutgoingRequestBridge]
gem5_system_port |
[OutgoingRequestBridge] ^ |
| |
[SSTResponder] v v [SSTResponder]
gem5 Component {SSTResponderSubComponent, SSTResponderSubComponent}
^ ^
| |
v v
================================== [SST Bus]
^
|
v
SST cache <----> SST memory
Components and SubComponents
-
gem5 Component has the following responsibilities,
- initializing the gem5 Python environment
- instantiating/setting-up the gem5 SimObjects as specified by the gem5 configuration
- connect every SSTResponderSubComponent to the corresponding OutgoingRequestBridge
- handling a gem5 event queue (with all thread-synchronization barriers removed)
- handling executions of gem5 events when it has clockTick yielded by SST Note: there should only be one gem5 Component per process.
-
SSTResponderSubComponent has the responsibity of receiving requests from gem5, translating requests to an SST Request and sending it to SSTResponder. Upon receiving a response from the memory interface, SSTResponderSubComponent will translate the response to a gem5 Packet and send it to the its OutgoingRequestBridge.
-
SSTResponder is owned by SSTResponderSubComponent. The responder will receive the request from the SubComponent and send it to the SST memory hierarchy.
Installation
See INSTALL.md.
Running an example simulation
Downloading the built bootloader containing a Linux Kernel and a workload,
wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
Running the simulation
sst sst/example.py
bbl-busybox-boot-exit contains an m5 binary, and m5 exit will be called
upon the booting process reaching the early userspace.
More information about building a bootloader containing a Linux Kernel and a
customized workload is available at
[https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/].
Notes
- SwapReq from gem5 requires reading from memory and writing to memory. We handle the request in SST in a way that, when SST gets the response from memory, SST will send that response to gem5, while SST will send a write request with modified data to memory.